SCHS196E September   1997  – October 2022 CD54HC688 , CD54HCT688 , CD74HC688 , CD74HCT688

PRODMIX  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|20
  • DW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Switching Characteristics

CL = 50pF. Input tr, tf = 6 ns
PARAMETER VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tPLH, tPHL

Propagation delay (Figure 6-1)

An to output

 2 170 210 255 ns
4.5 14(3) 34 42 51
6 29 36 43
tPLH, tPHL Bn to output 2 170 210 255 ns
4.5 14(3) 34 42 51
6 29 36 43
tPLH, tPHL E to output 2 120 150 180 ns
4.5 9(3) 24 30 36
6 20 26 30
tTLH, tTHL Output transition time (Figure 6-1) 2 75 95 110 ns
4.5 15 19 22
6 13 16 19
CIN Input capacitance 10 10 10 pF
CPD Power dissipation capacitance(1)(2) 22(4) pF
HCTTYPES
tPLH, tPHL

Propagation delay (Figure 6-1)

An to output

 4.5 14(3) 34 42 51 ns
tPLH, tPHL Bn to output 4.5 14(3) 34 42 51 ns
tPLH, tPHL E to output 4.5 9(3) 24 30 36 ns
tTLH, tTHL Output transition time (Figure 6-1) 4.5 15 19 22 ns
CIN Input capacitance 10 10 10 pF
CPD Power dissipation capacitance(1)(2) 5 22(4) pF
(1) CPD is used to determine the dynamic power consumption, per gate.
(2) PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
(3) CL = 15 pF and VCC = 5 V.
(4) CL = 15 pF.