SCHS136F August   1997  – February 2022 CD54HC85 , CD54HCT85 , CD74HC85 , CD74HCT85

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Specifications
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Buffered inputs and outputs
  • Typical propagation delay: 13 ns (data to output at VCC = 5 V, CL = 15 pF, TA = 25℃)
  • Serial or parallel expansion without external gating
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2 V to 6 V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility,
      VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1 μA at VOL, VOH