SCHS371H November   2009  – October 2024 CDC3RL02

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low Additive Noise
      2. 7.3.2 Regulated 1.8V Externally Available I/O Supply
      3. 7.3.3 Ultra-Small 8-bump YFP 0.4mm Pitch WCSP Package
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input Clock Squarer
      2. 8.1.2 Output Stage
      3. 8.1.3 LDO
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

CDC3RL02 YFP Package8-Pin DSBGATop ViewFigure 5-1 YFP Package8-Pin DSBGATop View
Table 5-1 Pin Functions
PIN Type(1) DESCRIPTION
NAME NO.
VBATT A1 I Input to internal LDO
CLK_OUT1 A2 O Clock output 1
VLDO B1 O 1.8V I/O supply for CDC3RL02 and external TCXO
CLK_REQ1 B2 I Clock request 1 (from peripheral) for Clock output 1
MCLK_IN C1 I Master clock input
CLK_REQ2 C2 I Clock request 2 (from peripheral) for Clock output 2
GND D1 – Ground
CLK_OUT2 D2 O Clock output 2
(1) I = Input, O = Output
Table 5-2 YFP Package Pin Assignments
1 2
A VBATT CLK_OUT1
B VLDO CLK_REQ1
C MCLK_LIN CLK_REQ2
D GND CLK_OUT2