SCES945 May   2022 CDCBT1001

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Down Tolerant Input
      2. 7.3.2 Up Conversion
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Processor Clock Up Translation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Clock frequency range: DC to 24 MHz
  • 1.2-V to 1.8-V LVCMOS clock level translation:
    • VDD_IN = 1.2 V ± 10%
    • VDD_OUT = 1.8 V ± 10%
  • Low additive jitter and phase noise:
    • 0.8-ps maximum 12-kHz to 5-MHz additive RMS jitter (fout = 24 MHz)
    • –120-dBc/Hz maximum phase noise at 1-kHz offset (fout = 24 MHz)
    • –148-dBc/Hz maximum phase noise floor (fout = 24 MHz, foffset ≥ 1 MHz)
  • 5-ns 20% to 80% rise/fall time
  • 10-ns propagation delay
  • Low current consumption
  • –40°C to 85°C operating temperature range