SCES945
May 2022
CDCBT1001
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power Down Tolerant Input
7.3.2
Up Conversion
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Processor Clock Up Translation
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Curve
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DPW|5
MPSS088
Thermal pad, mechanical data (Package|Pins)
DPW|5
QFND567C
Orderable Information
sces945_oa
sces945_pm
11.1.1
Related Documentation
For related documentation see the following:
Texas Instruments,
Implications of Slow or Floating CMOS Inputs
application report
Texas Instruments,
Designing and Manufacturing with TI's X2SON Packages
application report