SNAS833A November 2021 – May 2022 CDCDB400
PRODUCTION DATA
The SMBus address is assigned by configuring the SADR0 pin which is capable of supporting three levels. This configuration allows the CDCDB400 to assume three different SMBus addresses.
The SMBus address pin is sampled when PWRGD is set to 1. See Table 8-1 for address pin configuration. The address can only be changed by power cycling the device.
SADR0 | SMBus ADDRESS : WRITE OPERATION (READ/WRITE=0) | SMBus ADDRESS : READ OPERATION (READ/WRITE=1) |
---|---|---|
L | 0xD8 | 0xD9 |
M | 0xDA | 0xDB |
H | 0xDE | 0xDF |