SNAS833A November   2021  – May 2022 CDCDB400

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Input
      2. 8.3.2 Output Enable Control
      3. 8.3.3 SMBus
        1. 8.3.3.1 SMBus Address Assignment
    4. 8.4 Device Functional Modes
      1. 8.4.1 CKPWRGD_PD# Function
      2. 8.4.2 OE[3:0]# and SMBus Output Enables
      3. 8.4.3 Output Slew Rate Control
      4. 8.4.4 Output Impedance Control
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CDCDB400 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Enable Control Method
        2. 9.2.2.2 SMBus Address
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TICS Pro
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.1 CDCDB400 Registers

Table 8-4 lists the CDCDB400 registers. All register locations not listed in Table 8-4 should be considered as reserved locations and the register contents should not be modified.

Table 8-4 CDCDB400 Registers
Address Acronym Register Name Section
0h RCR1 Reserved Control Register 1 Go
1h OECR1 Output Enable Control 1 Go
2h OECR2 Output Enable Control 2 Go
3h OERDBK Output Enable# Pin Read Back Go
4h RCR2 Reserved Control Register 2 Go
5h VDRREVID Vendor/Revision Identification Go
6h DEVID Device Identification Go
7h BTRDCNT Byte Read Count Control Go
8h OUTSET Output Setting Control Go
4Ch CAPTRIM Slew Rate Capacitor Cluster 1 & 2 Go

Complex bit access types are encoded to fit into small table cells. Table 8-5 shows the codes that are used for access types in this section.

Table 8-5 CDCDB400 Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

8.6.1.1 RCR1 Register (Address = 0h) [reset = 47h]

RCR1 is shown in Table 8-6.

Return to the Summary Table.

The RCR1 register contains reserved bits.

Table 8-6 RCR1 Register Field Descriptions
BitFieldTypeResetDescription
7-4ReservedR4hReserved.
3-0ReservedR/W7h Writing to these bits will not affect the functionality of the device.

8.6.1.2 OECR1 Register (Address = 1h) [reset = FFh]

OECR1 is shown in Table 8-7.

Return to the Summary Table.

The OECR1 register contains bits that enable or disable individual output clock channels [1:0].

Table 8-7 OECR1 Register Field Descriptions
Bit Field Type Reset Description
7 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.
6 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.
5 OUT_EN_CLK1 R/W 1h This bit controls the output enable signal for output channel CK1_P/CK1_N.

0h = Output Disabled

1h = Output Enabled
4 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.
3 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.
2 OUT_EN_CLK0 R/W 1h This bit controls the output enable signal for output channel CK0_P/CK0_N.

0h = Output Disabled

1h = Output Enabled
1 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.
0 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.

8.6.1.3 OECR2 Register (Address = 2h) [reset = 0Fh]

OECR2 is shown in Table 8-8.

Return to the Summary Table.

The OECR2 register contains bits that enable or disable individual output clock channels [3:2].

Table 8-8 OECR2 Register Field Descriptions
Bit Field Type Reset Description
7-4 Reserved R/W 0h Writing to these bits will not affect the functionality of the device.
3 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.
2 OUT_EN_CLK3 R/W 1h This bit controls the output enable signal for output channel CK3_P/CK3_N.

0h = Output Disabled

1h = Output Enabled
1 Reserved R/W 1h Writing to this bit will not affect the functionality of the device.
0 OUT_EN_CLK2 R/W 1h This bit controls the output enable signal for output channel CK2_P/CK2_N.

0h = Output Disabled

1h = Output Enabled

8.6.1.4 OERDBK Register (Address = 3h) [reset = 0h]

OERDBK is shown in Table 8-9.

Return to the Summary Table.

The OERDBK register contains bits that report the current state of the OE[3:0]# input pins.

Table 8-9 OERDBK Register Field Descriptions
Bit Field Type Reset Description
7 RB_OEZ3 R 0h This bit reports the logic level present on the OE3# pin.
6 RB_OEZ2 R 0h This bit reports the logic level present on the OE2# pin.
5-4 Reserved R 0h Reserved.
3 RB_OEZ1 R 0h This bit reports the logic level present on the OE1# pin.
2 Reserved R 0h Reserved.
1 RB_OEZ0 R 0h This bit reports the logic level present on the OE0# pin.
0 Reserved R 0h Reserved.

8.6.1.5 RCR2 Register (Address = 4h) [reset = 0h]

RCR2 is shown in Table 8-10.

Return to the Summary Table.

The RCR2 register contains reserved bits.

Table 8-10 RCR2 Register Field Descriptions
Bit Field Type Reset Description
7-0 Reserved R 0h Reserved.

8.6.1.6 VDRREVID Register (Address = 5h) [reset = 0Ah]

VDRREVID is shown in Table 8-11.

Return to the Summary Table.

The VDRREVID register contains a vendor identification code and silicon revision code.
Table 8-11 VDRREVID Register Field Descriptions
Bit Field Type Reset Description
7-4 REV_ID R 0h Silicon revision code.
Silicon revision code bits
[3:0] map to register bits
[7:4] directly.
3-0 VENDOR_ID R Ah Vendor identification code.
Vendor ID bits
[3:0] map to register bits
[3:0] directly.

8.6.1.7 DEVID Register (Address = 6h) [reset = E7h]

DEVID is shown in Table 8-12.

Return to the Summary Table.

The DEVID register contains a device identification code.

Table 8-12 DEVID Register Field Descriptions
BitFieldTypeResetDescription
7-0DEV_IDRE7hDevice ID code.
Device ID bits[7:0] map to register bits[7:0] directly.

8.6.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]

BTRDCNT is shown in Table 8-13.

Return to the Summary Table.

The BTRDCNT register contains bits [4:0] which configure the number of bytes which will be read back.

Table 8-13 BTRDCNT Register Field Descriptions
Bit Field Type Reset Description
7-5 Reserved R/W 0h Writing to these bits will not affect the functionality of the device.
4 BYTE_COUNTER R/W 0h Writing to this register configures how many bytes will be read back.
3-0 BYTE_COUNTER R/W 8h

8.6.1.9 OUTSET Register (Address = 8h) [reset = 0h]

OUTSET is shown in Table 8-14.

Return to the Summary Table.

Bit5 of the OUTSET register sets the termination for all the outputs while bit4 can be used to set the power-down state for all outputs. The remaining bits for this register are reserved.

Table 8-14 OUTSET Register Field Descriptions
Bit Field Type Reset Description
7-6 Reserved R 0h Reserved.
5 CH_ZOUT_SEL R/W 0h Select between 85 Ω (0) and 100 Ω (1) Output impedance
4 d_DRIVE_OP_STATE_CTRL R/W 0h Power-down state of all output clocks.

0: LOW/LOW

1: TRI_STATE
3-0 Reserved R/W 0h Register bits can be written to 0. Writing a different value than 0 will affect device functionality.

8.6.1.10 CAPTRIM Register (Address = 4Ch) [reset = 66h]

CAPTRIM is shown in Table 8-16.

Return to the Summary Table.

Bits [7:4] of the CAPTRIM register is used to control the slew rate for output channel cluster 2. Bits [3:0] control the slew rate for output channel cluster 1. Refer below for cluster identification.

Table 8-15 Cluster Identification
Cluster Outputs
1 CK1, CK0
2 CK3, CK2
Table 8-16 CAPTRIM Register Field Descriptions
Bit Field Type Reset Description
7-4 CLUSTER2_CAP_TRIM R/W 6h Slew Rate Reduction Cap Trim for Cluster 2 Default value of 6h.

0: minimum

F: maximum
3-0 CLUSTER1_CAP_TRIM R/W 6h Slew Rate Reduction Cap Trim for Cluster 1. Default value of 6h.

0: minimum

F: maximum