SNAS818B July   2021  – May 2022 CDCDB800

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Input
      2. 8.3.2 Output Enable Control
      3. 8.3.3 SMBus
        1. 8.3.3.1 SMBus Address Assignment
    4. 8.4 Device Functional Modes
      1. 8.4.1 CKPWRGD_PD# Function
      2. 8.4.2 OE[7:0]# and SMBus Output Enables
      3. 8.4.3 Output Slew Rate Control
      4. 8.4.4 Output Impedance Control
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CDCDB800 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Enable Control Method
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TICS Pro
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions



Figure 5-1 CDCDB800 RSL Package48-Pin VQFNTop View
Table 5-1 Pin Functions CDCDB800
PIN TYPE(2)DESCRIPTION
NAMENO.
INPUT CLOCK
CLKIN_P4ILP-HCSL differential clock input. Typically connected directly to the differential output of clock source.
CLKIN_N5I
OUTPUT CLOCKS
CK0_P13OLP-HCSL differential clock output of channel 0. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK0_N14O
CK1_P16OLP-HCSL differential clock output of channel 1. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK1_N17O
CK2_P21OLP-HCSL differential clock output of channel 2. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK2_N

22

O
CK3_P25OLP-HCSL differential clock output of channel 3. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK3_N26O
CK4_P28OLP-HCSL differential clock output of channel 4. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK4_N29O
CK5_P32OLP-HCSL differential clock output of channel 5. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK5_N33O
CK6_P35OLP-HCSL differential clock output of channel 6. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK6_N36O
CK7_P39OLP-HCSL differential clock output of channel 7. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK7_N40O
MANAGEMENT AND CONTROL(1)
CKPWRGD_PD#1I, S, PDClock Power Good and Power Down multi-function input pin with internal 180-kΩ pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. After PWRGD has been asserted high for the first time, the pin becomes a PD# pin and it controls power-down mode:
LOW: Power-down mode, all output channels tri-stated.
HIGH: Normal operation mode.
OE0#
11I, S, PDOutput Enable for channel 0 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 0.
HIGH: disable output channel 0.
OE1#
18I, S, PDOutput Enable for channel 1 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 1.
HIGH: disable output channel 1.
OE2#23I, S, PDOutput Enable for channel 2 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 2.
HIGH: disable output channel 2.
OE3#24I, S, PDOutput Enable for channel 3, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 3.
HIGH: disable output channel 3.
OE4#30I, S, PDOutput Enable for channel 4, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 4.
HIGH: disable output channel 4.
OE5#
31I, S, PDOutput Enable for channel 5, with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 5.
HIGH: disable output channel 5.
OE6#37I, S, PDOutput Enable for channel 6 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 6.
HIGH: disable output channel 6.
OE7#41I, S, PDOutput Enable for channel 7 with internal 180-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect.
LOW: enable output channel 7.
HIGH: disable output channel 7.
SMBUS AND SMBUS ADDRESS
SMBDAT6I / OData pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k.
SMBCLK7IClock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k.

SMBWRTLOCK

46I, PDSMBWRTLOCK: Disables write commands on SMBus. All writes will be ignored when SMBWRTLOCK is asserted (reads are not affected). Internal 180-kΩ pulldown, active high.
0 = SMBus write enabled.
1 = SMBus write disabled.
SUPPLY VOLTAGE AND GROUND
GNDR2GGround.
VDDR3PPower supply input for input clock receiver. Connect to 3.3-V power supply rail with decoupling capacitor to GND. Place a 0.1-µF capacitor close to each supply pin between power supply and ground.
VDD10, 15, 19, 27, 34, 38, 42, 44P3.3-V power supply for output channels and core voltage.
GNDDAPGGround. Connect ground pad to system ground.
NO CONNECT
NC8, 9, 12, 20, 43, 45—Do not connect to GND or VDD.
NC47, 48—No connect. Pins may be connected to GND, VDD, or otherwise tied to any potential within the Supply Voltage range stated in the Absolute Maximum Ratings.
(1) The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage level. When “#” is not present, the signal is active high.
(2) The definitions below define the I/O type for each pin.
  • I = Input
  • O = Output
  • I / O = Input / Output
  • PU / PD = Internal 180-kΩ Pullup / Pulldown network biasing to VDD/2
  • PD = Internal 180-kΩ Pulldown
  • S = Hardware Configuration Pin
  • P = Power Supply
  • G = Ground