SNAS820A
August 2021 – May 2022
CDCDB803
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Fail-Safe Input
8.3.2
Output Enable Control
8.3.3
SMBus
8.3.3.1
SMBus Address Assignment
8.4
Device Functional Modes
8.4.1
CKPWRGD_PD# Function
8.4.2
OE[7:0]# and SMBus Output Enables
8.4.3
Output Slew Rate Control
8.4.4
Output Impedance Control
8.5
Programming
8.6
Register Maps
8.6.1
CDCDB803 Registers
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Output Enable Control Method
9.2.2.2
SMBus Address
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Examples
12
Device and Documentation Support
12.1
Device Support
12.1.1
TICS Pro
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RSL|48
MPQF193A
Thermal pad, mechanical data (Package|Pins)
RSL|48
QFND155N
Orderable Information
snas820a_oa
snas820a_pm
7
Parameter Measurement Information
Figure 7-1
AC Test Load (Referencing Intel DB2000QL Document)
R1 = 47 Ω and R2 = 147 Ω.
Figure 7-2
DC Simulation Load (Referencing Intel DB2000QL Document)