SNAS820A August   2021  – May 2022 CDCDB803

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Fail-Safe Input
      2. 8.3.2 Output Enable Control
      3. 8.3.3 SMBus
        1. 8.3.3.1 SMBus Address Assignment
    4. 8.4 Device Functional Modes
      1. 8.4.1 CKPWRGD_PD# Function
      2. 8.4.2 OE[7:0]# and SMBus Output Enables
      3. 8.4.3 Output Slew Rate Control
      4. 8.4.4 Output Impedance Control
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 CDCDB803 Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Enable Control Method
        2. 9.2.2.2 SMBus Address
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 TICS Pro
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ TA ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION
IDD_R Core supply current Active mode. CKPWRGD_PD# = 1 9 mA
Power-down mode. CKPWRGD_PD# = 0 2.2
IDD IO supply current All outputs disabled 18 mA
All outputs active, 100MHz (Per output) 7.8
Power-down mode. CKPWRGD_PD# = 0 1.5
CLOCK INPUT
fIN Input frequency 50 100 250 MHz
VIN Input voltage swing Differential voltage between CLKIN_P and CLKIN_N(1) 200 2300 mVDiff-peak
dV/dt Input voltage edge rate 20% - 80% of input swing 0.7 V/ns
DVCROSS Total variation of VCROSS Total variation across VCROSS 140 mV
DCIN Input duty cycle 40 60 %
CIN Input capacitance(2) Differential capacitance between CLKIN_P and CLKIN_N pins 2.2 pF
CLOCK OUTPUT
fOUT Output frequency 50 100 250 MHz
COUT Output capacitance(1) Differential capacitance between CKx_P and CKx_N pins 4 pF
VOH Output high voltage Single-ended(2) (3) 225 270 mV
VOL Output low voltage 10 150
VHIGH Output high voltage Measured into an AC load as defined in DB800ZL 660 850
VLOW Output low voltage Measured into an AC load as defined in DB800ZL –150 150
VMAX Output Max voltage Measured into an AC load as defined in DB800ZL 1150
VCROSS Crossing point voltage (3) (4) 130 200
VCROSSAC Crossing point voltage (AC load) Measured into an AC load as defined in DB800ZL 250 550
DVCROSS Total variation of VCROSS Variation of VCROSS (3) (4) 35 140
Vovs Overshoot voltage (3) VOH+75
Vovs(AC) Overshoot voltage (AC load) Measured into an AC load as defined in DB800ZL VHIGH+300
Vuds Undershoot voltage (3) VOL–75
Vuds(AC) Undershoot voltage Measured into an AC load as defined in DB800ZL VLOW–300 mV
Vrb Ringback Voltage Measured into an AC load as defined in DB800ZL and taken from Single Ended waveform (relative to VHIGH  and VLOW) -0.2 0.2 V
ZDIFF Differential impedance (Default setting, 85 Ω) Measured at VOL/VOH 81 85 89 Ω
Differential impedance (Output impedance selection bit =1, 100 Ω)  Measured at VOL/VOH 95 100 105
ZDIFF_CROSS Differential impedance (Default setting, 85 Ω) Measured at VCROSS 68 85 102
Differential impedance (Output impedance selection bit = 1, 100 Ω) Measured at VCROSS 80 100 120
tEDGE Differential edge rate Measured (+-150 mV) around VCROSS (7) 2 4 V/ns
DtEDGE Edge rate matching Measured (+-75 mV) VCROSS (7) 20 %
tSTABLE Power good assertion to stable clock output CKPWRGD_PD# pin transitions from 0 to 1, fIN = 100 MHz Measured when positive output reaches 0.2V 1.8 ms
tDRIVE_PD# Power good assertion to outputs driven high CKPWRGD_PD# pin transitions from 0 to 1, fIN = 100 MHz Measured when positive output reaches 0.2V 300 µs
tOE Output enable assertion to stable clock output OEx# pin transitions from 1 to 0 10 CLKIN Periods
tOD Output enable de-assertion to no clock output OEx# pin transitions from 0 to 1 10
tPD Power-down assertion to no clock output CKPWRGD_PD# pin transitions from 1 to 0 3
tDCD Duty cycle distortion Differential; fIN = 100MHz, fIN_DC = 50% –1 1 %
tDLY Propagation delay (5) 0.5 3 ns
tSKEW Skew between outputs (6) 50 ps
tDELAY(IN-OUT) Input to output delay variation Input-to-output delay variation at 100 MHz across voltage and temperature –250 250 ps
JCKx_DB2000Q (7) Additive jitter for DB2000Q DB2000Q filter, for input of 200 mV differential swing @ 1.5 V/ns 0.038 ps, RMS
JCKx_PCIE (7) Additive jitter for PCIe6.0 PLL BW: 0.5 - 1 MHz; CDR = 10 MHz Input clock slew rate = 2 V/ns 0.02 ps, RMS
Additive jitter for PCIe5.0 PCIe5.0 filter 0.025
Additive jitter for PCIe4.0 PLL BW = 2 - 5 MHz; CDR = 10 MHz Input clock slew rate ≥ 1.8 V/ns 0.06
Additive jitter for PCIe3.0 Input clock slew rate ≥ 0.6 V/ns 0.1
JCKx Additive jitter fIN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to 20 MHz integration bandwidth. 100 160 fs, RMS
NF Noise floor fIN = 100 MHz; fOffset ≥ 10 MHz Input clock slew rate ≥ 3 V/ns –160 -155 dBc/Hz
SMBUS INTERFACE, OEx#, CKPWRGD_PD#
VIH High level input voltage 2.0 V
VIL Low level input voltage 0.8
IIH Input leakage current With internal pull-up/pull-down GND ≤ VIN ≤ VDD –30 30 µA
IIL Input leakage current With internal pull-up/pull-down GND ≤ VIN ≤ VDD –30 30 µA
IIH Input leakage current Without internal pull-up/pull-down GND ≤ VIN ≤ VDD −5 5 µA
IIL Input leakage current Without internal pull-up/pull-down GND ≤ VIN ≤ VDD −5 5 µA
CIN Input capacitance 4.5 pF
COUT Output capacitance 4.5 pF
3-LEVEL DIGITAL INTERFACE (SADR0, SADR1)
VIH High level input voltage 2.3 V
VIM Mid level input voltage 1.25 VDD/2 1.725
VIL Low level input voltage 0.85
IIH Input leakage current With internal pull-up/pull-down VIN = VDD –30 30 µA
IIL Input leakage current With internal pull-up/pull-down VIN = GND –30 30 µA
CIN Input capacitance(1) 4.5 pF
(1) Voltage swing includes overshoot.
(2) Not tested in production. Ensured by design and characterization.
(3) Measured into DC test load.
(4) VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P is rising.
(5) Measured from rising edge of CLK_IN to any CKx output.
(6) Measured from rising edge of any CKx output to any other CKx output.
(7) Measured into AC test load.