SCAS882E June   2009  – October 2016 CDCE62002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Thermal Information
    3. 7.3 Electrical Characteristics
    4. 7.4 Timing Requirements
    5. 7.5 SPI Bus Timing Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
      1. 9.2.1 Interface and Control Block
      2. 9.2.2 Input Block
      3. 9.2.3 Output Block
      4. 9.2.4 Synthesizer Block
      5. 9.2.5 Computing the Output Frequency
    3. 9.3 Feature Description
      1. 9.3.1 Phase Noise Analysis
      2. 9.3.2 Output-to-Output Isolationthe OUTPUT TO OUTPUT ISOLATION section
      3. 9.3.3 Device Control
      4. 9.3.4 External Control Pins
        1. 9.3.4.1 Factory Default Programming
      5. 9.3.5 Input Block
        1. 9.3.5.1 Reference Input Buffer
        2. 9.3.5.2 Smart Multiplexer Dividers
        3. 9.3.5.3 Auxiliary Input Port
        4. 9.3.5.4 Output Block
        5. 9.3.5.5 Synthesizer Block
        6. 9.3.5.6 Input Divider
        7. 9.3.5.7 Feedback and Feedback Bypass Divider
          1. 9.3.5.7.1 VCO Select
          2. 9.3.5.7.2 Prescaler
          3. 9.3.5.7.3 Loop Filter
        8. 9.3.5.8 Internal Loop Filter Component Configuration
      6. 9.3.6 Lock Detect
      7. 9.3.7 Crystal Input Interface
      8. 9.3.8 VCO Calibration
      9. 9.3.9 Start-Up Time Estimation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Clock Generator
      2. 9.4.2 SERDES Start-Up and Clock Cleaner
      3. 9.4.3 Clocking ADCS With the CDCE62002
    5. 9.5 Programming
      1. 9.5.1 Interface and Control Block
        1. 9.5.1.1 SPI (Serial Peripheral Interface)
        2. 9.5.1.2 SPI Interface Master
        3. 9.5.1.3 SPI Consecutive Read/Write Cycles to the CDCE62002
        4. 9.5.1.4 Writing to the CDCE62002
        5. 9.5.1.5 Reading from the CDCE62002
        6. 9.5.1.6 Writing to EEPROM
        7. 9.5.1.7 CDCE62002 SPI Command Structure
      2. 9.5.2 Device Configuration
    6. 9.6 Register Maps
      1. 9.6.1 Device Registers: Register 0 Address 0x00
      2. 9.6.2 Device Registers: Register 1 Address 0x01
      3. 9.6.3 Device Registers: Register 2 Address 0x02
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

RHB Package
32-Pin QFN
Top View
CDCE62002 po_cas882.gif

Pin Functions

PIN TYPE DESCRIPTION(1)
NAME NO.
AUX_IN 2 I Auxiliary Input is a Crystal input pin that connect to an internal oscillator circuitry.
EXT_LFN 26 Analog External Loop Filter Input Negative.
EXT_LFP 25 Analog External Loop Filter Input Positive
GND PAD Ground Ground is on Thermal PAD. See Layout Guidelines
GND_PLLDIV 21 Ground Ground for PLL Divider circuitry. (short to GND)
PD 6 I PD or Power-Down Pin is an active low pin and can be activated externally or through the corresponding Bit in SPI Register 2
While PD is asserted (low), the device is shut down. When PD switches high the EEPROM becomes loaded into the RAM. After the selected input clock signal becomes available, the VCO starts calibration and the PLL aims to achieve lock. All Output dividers become initiated. During self-calibration, the outputs are held static (for example, logical zero). PD pin has an internal 150-kΩ pullup resistor. Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly into RAM on the Rising edge of PD.
PLL_LOCK 32 O PLL Lock indicator
REF_IN+ 29 I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Reference Clock.
REF_IN– 30 I Universal Input Buffer (LVPECL, LVDS,) negative input for the Reference Clock. This pin must be pulled to ground through 1-kΩ resistor when input is selected LVCMOS.
REG_CAP1 5 Analog Capacitor for the internal Regulator. Connect to a 10-μF Capacitor (Y5V)
REG_CAP2 27 Analog Capacitor for the internal Regulator. Connect to a 10-μF Capacitor (Y5V)
REG_CAP3 20 Analog Capacitor for the internal Regulator. Connect to a 10-μF Capacitor (Y5V)
REG_CAP4 23 Analog Capacitor for the internal Regulator. Connect to a 10-μF Capacitor (Y5V)
SPI_CLK 17 I LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis.
SPI_LE 18 I LVCMOS input, control Latch Enable for Serial Programmable Interface.
Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly on the Rising edge of PD. The input has an internal 150-kΩ pull-up resistor
SPI_MISO 7 O 3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial Data Output to the SPI bus interface.
SPI_MOSI 8 I LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62002 for the SPI bus interface.
TESTSYNC 19 I Reserved Pin. Pull this pin down to ground using 1-kΩ resistor.
U0P:U0N
U1P:U1N		 11,10
15,14		 O The outputs of CDCE62002 are user definable and can be any combination of up to 2 LVPECL outputs, 2 LVDS outputs or up to 4 LVCMOS outputs. The outputs are selectable through SPI interface. The power-up setting is EEPROM configurable.
VBB 3 Analog Capacitor for the internal termination Voltage. Connect to a 1-μF Capacitor (Y5V)
VCC_AUX 1 A. Power 3.3-V Supply Power for Crystal/Auxiliary Input Buffer Circuitry
VCC_IN 31 A. Power 3.3-V Supply Power for Input Buffer Circuitry
VCC_OUT0 9, 12 Power 3.3-V Supply for the Output Buffers.
VCC_OUT1 13, 16
VCC_PLLA 28 A. Power 3.3-V Supply Power for the PLL circuitry.
VCC_PLLD 4 Power 3.3-V Supply Power for the PLL circuitry.
VCC_PLLDIV 22 Power 3.3-V Supply Power for the PLL circuitry.
VCC_VCO 24 A. Power 3.3-V Supply Power for the VCO circuitry.
(1) It is furthermore recommended to use a supply filter for each VCC supply domain independently. A minimum requirement is to group the supplies into four independent groups:
VCC_PLLA + VCC_VCO
VCC_PLLD + VCC_PLLDIV
VCC_IN + VCC_AUXIN
VCC_OUT0 + VCC_OUT1
All VCC pins need to be connected for the device to operate properly.