SNAS852
june 2023
CDCE6214Q1TM
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Revision History
5
Description (cont.)
6
Device Comparison
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
EEPROM Characteristics
8.6
Reference Input, Single-Ended Characteristics
8.7
Reference Input, Differential Characteristics
8.8
Reference Input, Crystal Mode Characteristics
8.9
General-Purpose Input Characteristics
8.10
Triple Level Input Characteristics
8.11
Logic Output Characteristics
8.12
Phase Locked Loop Characteristics
8.13
Closed-Loop Output Jitter Characteristics
8.14
Input and Output Isolation
8.15
Buffer Mode Characteristics
8.16
PCIe Spread Spectrum Generator
8.17
LVCMOS Output Characteristics
8.18
LP-HCSL Output Characteristics
8.19
LVDS Output Characteristics
8.20
Output Synchronization Characteristics
8.21
Power-On Reset Characteristics
8.22
I2C-Compatible Serial Interface Characteristics
8.23
Timing Requirements, I2C-Compatible Serial Interface
8.24
Power Supply Characteristics
8.25
Typical Characteristics
9
Parameter Measurement Information
9.1
Reference Inputs
9.2
Outputs
9.3
Serial Interface
9.4
PSNR Test
9.5
Clock Interfacing and Termination
9.5.1
Reference Input
9.5.2
Outputs
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Reference Block
10.3.1.1
Zero Delay Mode, Internal and External Path
10.3.2
Phase-Locked Loop (PLL)
10.3.2.1
PLL Configuration and Divider Settings
10.3.2.2
Spread Spectrum Clocking
10.3.2.3
Digitally-Controlled Oscillator and Frequency Increment or Decrement - Serial Interface Mode and GPIO Mode
10.3.3
Clock Distribution
10.3.3.1
Glitchless Operation
10.3.3.2
Divider Synchronization
10.3.3.3
Global and Individual Output Enable
10.3.4
Power Supplies and Power Management
10.3.5
Control Pins
10.4
Device Functional Modes
10.4.1
Operation Modes
10.4.1.1
Fall-Back Mode
10.4.1.2
Pin Mode
10.4.1.3
Serial Interface Mode
10.5
Programming
10.5.1
I2C Serial Interface
10.5.2
EEPROM
10.5.2.1
EEPROM - Cyclic Redundancy Check
10.5.2.2
Recommended Programming Procedure
10.5.2.3
EEPROM Access
10.5.2.3.1
Register Commit Flow
10.5.2.3.2
Direct Access Flow
10.5.2.4
Register Bits to EEPROM Mapping
11
Application and Implementation
11.1
Application Information
11.2
Typical Application
11.2.1
Design Requirements
11.2.2
Detailed Design Procedure
11.2.3
Application Curves
11.3
Power Supply Recommendations
11.3.1
Power-Up Sequence
11.3.2
Decoupling
11.4
Layout
11.4.1
Layout Guidelines
11.4.2
Layout Examples
12
Device and Documentation Support
12.1
Device Support
12.1.1
Development Support
12.1.2
Device Nomenclature
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RGE|24
MPQF124G
Thermal pad, mechanical data (Package|Pins)
RGE|24
QFND593
Orderable Information
snas852_oa
snas852_pm
Data Sheet
CDCE6214Q1TM
Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM