VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°CPARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
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fPFD | Phase Detector Frequency | Integer and Fractional PLL mode | 1 | | 100 | MHz |
fVCO | Voltage Controlled Oscillator Frequency | | 2335 | | 2625 | MHz |
fBW | Configurable closed-loop PLL Bandwidth | REF = 25 MHz | 100 | | 1600 | kHz |
KVCO | Voltage-Controlled Oscillator Gain | fVCO = 2.4 GHz | | 140 | | MHz/V |
KVCO | Voltage-Controlled Oscillator Gain | fVCO = 2.5 GHz | | 175 | | MHz/V |
|ΔTCL| | Allowable Temperature Drift for Continuous Lock(1) | dT/dt ≤ 20 K / min | | | 145 | oC |
fMAX-ERROR | Maximum frequency error with frac-N PLL | | | | 0.1 | ppm |
(1) The maximum allowable temperature drift for continuous lock: how far the temperature can drift in either direction from the value it was at the time, when the On-Chip VCO was calibrated while the PLL stays in lock throughout the temperature drift. The internal VCO calibration takes place: at device start-up, when the device is reset using the RESET pin and when REGISTER bit is changed. This implies the device will work over the entire frequency range, but if the temperature drifts more than the 'maximum allowable temperature drift for continuous lock', then it is necessary to re-calibrate the VCO, using the appropriate REGISTER bit, to ensure the PLL stays in lock. Regardless of what temperature the part was initially calibrated at, the temperature can never drift outside the ambient temperature range of -40° C to 105° C.