SNAS852 june   2023 CDCE6214Q1TM

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  EEPROM Characteristics
    6. 8.6  Reference Input, Single-Ended Characteristics
    7. 8.7  Reference Input, Differential Characteristics
    8. 8.8  Reference Input, Crystal Mode Characteristics
    9. 8.9  General-Purpose Input Characteristics
    10. 8.10 Triple Level Input Characteristics
    11. 8.11 Logic Output Characteristics
    12. 8.12 Phase Locked Loop Characteristics
    13. 8.13 Closed-Loop Output Jitter Characteristics
    14. 8.14 Input and Output Isolation
    15. 8.15 Buffer Mode Characteristics
    16. 8.16 PCIe Spread Spectrum Generator
    17. 8.17 LVCMOS Output Characteristics
    18. 8.18 LP-HCSL Output Characteristics
    19. 8.19 LVDS Output Characteristics
    20. 8.20 Output Synchronization Characteristics
    21. 8.21 Power-On Reset Characteristics
    22. 8.22 I2C-Compatible Serial Interface Characteristics
    23. 8.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 8.24 Power Supply Characteristics
    25. 8.25 Typical Characteristics
  10. 9 Parameter Measurement Information
    1. 9.1 Reference Inputs
    2. 9.2 Outputs
    3. 9.3 Serial Interface
    4. 9.4 PSNR Test
    5. 9.5 Clock Interfacing and Termination
      1. 9.5.1 Reference Input
      2. 9.5.2 Outputs
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Reference Block
        1. 10.3.1.1 Zero Delay Mode, Internal and External Path
      2. 10.3.2 Phase-Locked Loop (PLL)
        1. 10.3.2.1 PLL Configuration and Divider Settings
        2. 10.3.2.2 Spread Spectrum Clocking
        3. 10.3.2.3 Digitally-Controlled Oscillator and Frequency Increment or Decrement - Serial Interface Mode and GPIO Mode
      3. 10.3.3 Clock Distribution
        1. 10.3.3.1 Glitchless Operation
        2. 10.3.3.2 Divider Synchronization
        3. 10.3.3.3 Global and Individual Output Enable
      4. 10.3.4 Power Supplies and Power Management
      5. 10.3.5 Control Pins
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operation Modes
        1. 10.4.1.1 Fall-Back Mode
        2. 10.4.1.2 Pin Mode
        3. 10.4.1.3 Serial Interface Mode
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 EEPROM
        1. 10.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 10.5.2.2 Recommended Programming Procedure
        3. 10.5.2.3 EEPROM Access
          1. 10.5.2.3.1 Register Commit Flow
          2. 10.5.2.3.2 Direct Access Flow
        4. 10.5.2.4 Register Bits to EEPROM Mapping
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
      1. 11.3.1 Power-Up Sequence
      2. 11.3.2 Decoupling
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Layout Examples
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

GUID-F354ACFC-9ACF-4E6D-BB35-FC7236D70179-low.svg Figure 7-1 RGE Package24-Pin VQFNTop View
Table 7-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
POWER
DAP — G Die Attach Pad. The DAP is an electrical connection and provides a thermal dissipation path. For proper electrical and thermal performance of the device, the DAP must be connected to PCB ground plane.
VDD_REF 3 P 1.8-V, 2.5-V, or 3.3-V Power Supply for Reference Input and Digital.
VDD_VCO 24 P 1.8-V, 2.5-V, or 3.3-V Power Supply for PLL/VCO.
VDDO_12 16 P 1.8-V, 2.5-V, or 3.3-V Power Supply for OUT1 and OUT2 channels
VDDO_34 15 P 1.8-V, 2.5-V, or 3.3-V Power Supply for OUT0, OUT3, and OUT4 channels
INPUT BLOCK
HW_SW_CTRL 23 I, RPUPD Manual selection pin for EEPROM pages (tri-state). Weak Pullup/Pulldown. RPU = 50 kΩ. RPD = 50 kΩ.
PRIREF_P 5 I Primary reference clock. Accepts a differential or single-ended input. Input pins need AC-coupling capacitors and internally biased in differential mode. For LVCMOS, input should be provided on PRIREF_P and the non-driven input pin should be pulled down to ground. Internal biasing for differential mode is disabled in single-ended mode.
PRIREF_N 6 I
REFSEL 4 I, RPUPD Manual selection pin of reference input (tri-state). Weak Pullup/Pulldown. RPU = 50 kΩ. RPD = 50 kΩ.
SECREF_P 1 I Secondary reference clock. Accepts a differential or single-ended input or XTAL. Input pins need AC-coupling capacitors and internally biased in differential mode. For XTAL input, connect crystal between SECREF_P and SECREF_N pin. SECREF_P is XOUT, SECREF_N is XIN. This device do not need any power limiting resistor on XOUT. For LVCMOS input, input should be provided on SECREF_P, and the non-driven input pin should be pulled down to ground. Internal biasing for differential mode is disabled in single-ended and XTAL mode.
SECREF_N 2 I
OUTPUT BLOCK
OUT0 7 O LVCMOS Output 0. Reference Input can be bypassed into this output. Output slew-rate configurable on all LVCMOS outputs.
OUT1_P 22 O LVDS-like/LP-HCSL/LVCMOS Output Pair 1. Programmable driver with LVDS-like/LP-HCSL or 2x LVCMOS outputs.
OUT1_N 21 O
OUT2_P 18 O LVDS-like/LP-HCSL Output Pair 2. Programmable driver with LVDS-like/LP-HCSL outputs.
OUT2_N 17 O
OUT3_P 14 O LVDS-like/LP-HCSL Output Pair 3. Programmable driver with LVDS-like/LP-HCSL outputs.
OUT3_N 13 O
OUT4_P 10 O LVDS-like/LP-HCSL/LVCMOS Output Pair 4. Programmable driver with LVDS-like/LP-HCSL or 2x LVCMOS outputs.
OUT4_N 9 O
DIGITAL CONTROL / INTERFACES
GPIO1 20 I/O STATUS output or GPIO1 input.
GPIO4 11 I/O STATUS output or GPIO4 input.
PDN 8 I, RPU Device Power-down/RESET (active low) or SYNCN. Weak pullup resistor. RPU = 50 kΩ. Pullup resistor disabled in output mode.
SDA/GPIO2 19 I/O I2C Serial Data (bidirectional, open-drain) or GPIO2 input. Requires an external pullup resistor to VDD_REF in I2C mode. I2C address is initialized from on-chip EEPROM. Fail-safe Input.
SCL/GPIO3 12 I I2C Serial Clock or GPIO3 input. Requires an external pullup resistor to VDD_REF in I2C mode. Fail-safe Input.
(1) Type:
  • G = Ground
  • P = Power
  • I = Input
  • I/O = Input/Output
  • O = Output
  • I, RPUPD = Input with Resistive Pullup and Pulldown
  • I, RPU = Input with Resistive Pullup
  • I/O, RPU = Input/Output with Resistive Pullup