SNAS852 june   2023 CDCE6214Q1TM

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  EEPROM Characteristics
    6. 8.6  Reference Input, Single-Ended Characteristics
    7. 8.7  Reference Input, Differential Characteristics
    8. 8.8  Reference Input, Crystal Mode Characteristics
    9. 8.9  General-Purpose Input Characteristics
    10. 8.10 Triple Level Input Characteristics
    11. 8.11 Logic Output Characteristics
    12. 8.12 Phase Locked Loop Characteristics
    13. 8.13 Closed-Loop Output Jitter Characteristics
    14. 8.14 Input and Output Isolation
    15. 8.15 Buffer Mode Characteristics
    16. 8.16 PCIe Spread Spectrum Generator
    17. 8.17 LVCMOS Output Characteristics
    18. 8.18 LP-HCSL Output Characteristics
    19. 8.19 LVDS Output Characteristics
    20. 8.20 Output Synchronization Characteristics
    21. 8.21 Power-On Reset Characteristics
    22. 8.22 I2C-Compatible Serial Interface Characteristics
    23. 8.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 8.24 Power Supply Characteristics
    25. 8.25 Typical Characteristics
  10. 9 Parameter Measurement Information
    1. 9.1 Reference Inputs
    2. 9.2 Outputs
    3. 9.3 Serial Interface
    4. 9.4 PSNR Test
    5. 9.5 Clock Interfacing and Termination
      1. 9.5.1 Reference Input
      2. 9.5.2 Outputs
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Reference Block
        1. 10.3.1.1 Zero Delay Mode, Internal and External Path
      2. 10.3.2 Phase-Locked Loop (PLL)
        1. 10.3.2.1 PLL Configuration and Divider Settings
        2. 10.3.2.2 Spread Spectrum Clocking
        3. 10.3.2.3 Digitally-Controlled Oscillator and Frequency Increment or Decrement - Serial Interface Mode and GPIO Mode
      3. 10.3.3 Clock Distribution
        1. 10.3.3.1 Glitchless Operation
        2. 10.3.3.2 Divider Synchronization
        3. 10.3.3.3 Global and Individual Output Enable
      4. 10.3.4 Power Supplies and Power Management
      5. 10.3.5 Control Pins
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operation Modes
        1. 10.4.1.1 Fall-Back Mode
        2. 10.4.1.2 Pin Mode
        3. 10.4.1.3 Serial Interface Mode
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 EEPROM
        1. 10.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 10.5.2.2 Recommended Programming Procedure
        3. 10.5.2.3 EEPROM Access
          1. 10.5.2.3.1 Register Commit Flow
          2. 10.5.2.3.2 Direct Access Flow
        4. 10.5.2.4 Register Bits to EEPROM Mapping
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
      1. 11.3.1 Power-Up Sequence
      2. 11.3.2 Decoupling
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Layout Examples
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3.2 Phase-Locked Loop (PLL)

The CDCE6214Q1TM has a fully-integrated Phase-Locked Loop (PLL) circuit. The error between a reference phase and an internal feedback phase is compared at the phase-frequency detector. The comparison result is fed to a charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes an internal voltage-controlled oscillator (VCO). The frequency of the VCO is fed through a feedback divider (N-counter) back to the PFD.

  • Integer and Fractional-N PLL mode of operation.
  • First-, Second-, or Third-Order MASH operation in Fractional mode.
  • 24-bit Numerator and Denominator can be used to generate fractional frequencies with 0 ppb frequency accuracy.
  • PFD operates between 1 MHz and 100 MHz.
  • Live Lock Detector (R7[0] or PLL_LOCK in GPIO) provides PLL Lock status (in fractional mode and SSC enabled, lock detect window must be widened. R50[10:8] = 7h). Additionally, sticky bit lock detect (R7[1]) detects if there was any temporary loss of lock.
  • Integrated selectable loop filter components.
  • For a 25-MHz PFD frequency, PFD bandwidth between 100 kHz and 1.6 MHz can be achieved to optimize PLL to input reference.
  • Voltage-controlled oscillator (VCO) ranges from 2335 MHz to 2615 MHz.
  • Supports 0.25% and 0.5% center and down spread Spread Spectrum Clocking (SSC) generation. Further, VCO also supports up to 0.5% SSC references at 100 MHz for PCIe clocking.

Table 10-3 Common Clock Generator Loop Filter Settings
fVCO IN MHzfPFD IN MHzBW IN MHzPHASE MARGIN IN °DAMPING FACTORICP IN mACPcap IN pFRRes IN kΩCZcap IN pF
2400250.469700.50.6016.12.5580
2400500.9387020.608.22.5276
24001001.60700.50.808.22.5303
2457.661.441.04701.150.609.22.0331
2500250.49700.40.6013.52.5497
2500500.93701.00.6011.72.5386
240050400650.10.4011.71.5636
Table 10-4 Common PLL Divider Settings (1)
INPUT FREQUENCY IN MHzfPFD IN MHzOUTPUT FREQUENCY IN MHzfVCON-COUNTER DIVIDER VALUENUMERATORDENOMINATORPSAOUTPUT DIVIDER
2550100240048NANA46
2525100240096NANA46
2550156.25250050NANA44
252525240096NANA424
252524.5762457.698507161416682942425
2525148.52376956649831662457944
1. Fractional Mode settings are based on DCO mode step size of 0.1 ppm