VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and TA = -40°C to 105°CPARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
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VTHRESHOLD | POR threshold voltage(1) | | 0.875 | | 1.275 | V |
tSTARTUP | Start-up time | Start-up time after VDD reaches 95% to the time outputs are toggling with correct frequency (input = crystal or external clock) | | 9 | | ms |
tVDD | Power supply ramp time(2) | timing requirement for any VDD pin while PDN=LOW | 0.1 | | 30 | ms |
(1) POR threshold voltage is the power supply voltage at which the internal reset is deasserted. It is qualified internally with PDN.
(2) VDD pin should monotonically reach 95% of its final value within supply ramp time. Parameters specified by characterization. All VDD pins were tied together for this evaluation. For non-monotonic or slower power supply ramp, it is recommended to pull-down PDN pin until VDD pins have reached 95% of its final value. PDN pin has a 50 kΩ pullup resistor. When PDN pin cannot be actively controlled, TI recommends to add a capacitor to GND on PDN pin to delay the release of reset.