SNAS852 june   2023 CDCE6214Q1TM

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (cont.)
  7. 6 Device Comparison
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  EEPROM Characteristics
    6. 8.6  Reference Input, Single-Ended Characteristics
    7. 8.7  Reference Input, Differential Characteristics
    8. 8.8  Reference Input, Crystal Mode Characteristics
    9. 8.9  General-Purpose Input Characteristics
    10. 8.10 Triple Level Input Characteristics
    11. 8.11 Logic Output Characteristics
    12. 8.12 Phase Locked Loop Characteristics
    13. 8.13 Closed-Loop Output Jitter Characteristics
    14. 8.14 Input and Output Isolation
    15. 8.15 Buffer Mode Characteristics
    16. 8.16 PCIe Spread Spectrum Generator
    17. 8.17 LVCMOS Output Characteristics
    18. 8.18 LP-HCSL Output Characteristics
    19. 8.19 LVDS Output Characteristics
    20. 8.20 Output Synchronization Characteristics
    21. 8.21 Power-On Reset Characteristics
    22. 8.22 I2C-Compatible Serial Interface Characteristics
    23. 8.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 8.24 Power Supply Characteristics
    25. 8.25 Typical Characteristics
  10. 9 Parameter Measurement Information
    1. 9.1 Reference Inputs
    2. 9.2 Outputs
    3. 9.3 Serial Interface
    4. 9.4 PSNR Test
    5. 9.5 Clock Interfacing and Termination
      1. 9.5.1 Reference Input
      2. 9.5.2 Outputs
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Reference Block
        1. 10.3.1.1 Zero Delay Mode, Internal and External Path
      2. 10.3.2 Phase-Locked Loop (PLL)
        1. 10.3.2.1 PLL Configuration and Divider Settings
        2. 10.3.2.2 Spread Spectrum Clocking
        3. 10.3.2.3 Digitally-Controlled Oscillator and Frequency Increment or Decrement - Serial Interface Mode and GPIO Mode
      3. 10.3.3 Clock Distribution
        1. 10.3.3.1 Glitchless Operation
        2. 10.3.3.2 Divider Synchronization
        3. 10.3.3.3 Global and Individual Output Enable
      4. 10.3.4 Power Supplies and Power Management
      5. 10.3.5 Control Pins
    4. 10.4 Device Functional Modes
      1. 10.4.1 Operation Modes
        1. 10.4.1.1 Fall-Back Mode
        2. 10.4.1.2 Pin Mode
        3. 10.4.1.3 Serial Interface Mode
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 EEPROM
        1. 10.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 10.5.2.2 Recommended Programming Procedure
        3. 10.5.2.3 EEPROM Access
          1. 10.5.2.3.1 Register Commit Flow
          2. 10.5.2.3.2 Direct Access Flow
        4. 10.5.2.4 Register Bits to EEPROM Mapping
  12. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
    3. 11.3 Power Supply Recommendations
      1. 11.3.1 Power-Up Sequence
      2. 11.3.2 Decoupling
    4. 11.4 Layout
      1. 11.4.1 Layout Guidelines
      2. 11.4.2 Layout Examples
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3.3 Clock Distribution

The VCO output connects to two individually configurable pre-scalar dividers sourcing the on-chip clock distribution – PSA and PSB. PSA and PSB can be configured as division value of /4, /5 or /6 independently.

The clock distribution consists of four output channels. Each output channel contains an integer divider (IOD) with glitchless switching and synchronization capabilities.

IOD can be sourced from either the PSA, the PSB, or the Reference Clock. IOD can be bypassed to provide a Reference clock at the output.

There are five output channels – OUT0, OUT1, OUT2, OUT3, and OUT4.

The OUT0 is a slew-rate controllable LVCMOS output. Either the reference clock or PFD clock can be routed to this output through the clock distribution network.

The OUT1 and OUT4 are identical output channels. The output buffers in this channel are compatible with various signaling standards – LVCMOS, LP-HCSL, and LVDS-like.

The OUT2 and OUT3 are identical output channels. The output buffers in this channel are compatible with various signaling standards – LP-HCSL and LVDS-like.

  • The LP-HCSL output buffer can be directly connected to the receiver without any termination resistor to GND. The output impedance of LP-HCSL is trimmed to 50 Ω ± 10%. A series resistor can be used to adapt to the trace impedance.
  • The LVDS-like requires a differential termination connected between the positive and negative polarity output pins. The termination can be connected directly or through an AC-coupling capacitor. For a 50-Ω system, a 100-Ω differential termination is appropriate.
  • LVCMOS outputs are designed for capacitive loads only. The polarity of the positive and negative output pins can be configured individually.
The differential buffers support wide range of output frequencies up to 328.125 MHz. LVCMOS supports up to 200 MHz.

Table 10-9 Configuring Input Reference, PFD, or PLL Clock to Output(1)
REGISTER BIT ADDRESSREGISTER BIT FIELD NAMEDESCRIPTION
R25[10]IP_BYP_OUT0_ENEnables Reference Clock or PFD Clock to OUT0.
R25[9]REF_CH_MUXSelects between PFD Clock or Input Reference Clock
R25[14:11]IP_REF_TO_OUT4_EN, IP_REF_TO_OUT3_EN, IP_REF_TO_OUT2_EN, IP_REF_TO_OUT1_ENSelects reference clock to OUT1-OUT4
R56[15:14]CH1_MUXClock selection MUX control for OUT1
R62[15:14]CH2_MUXClock selection MUX control for OUT2
R67[15:14]CH3_MUXClock selection MUX control for OUT3
R72[15:14]CH4_MUXClock selection MUX control for OUT4
(1) TI recommends to disable any clock when not in use to reduce crosstalk
Table 10-10 Configuring Clock Distribution Network
REGISTER BIT ADDRESSREGISTER BIT FIELD NAMEDESCRIPTION
R47[6:5]PLL_PSBProgrammable Pre-scalar divider PSB
R47[4:3]PLL_PSAProgrammable Pre-scalar divider PSA
R56[13:0]CH1_DIVOUT1 Integer Divider value
R62[13:0]CH2_DIVOUT2 Integer Divider value
R67[13:0]CH3_DIVOUT3 Integer Divider value
R72[13:0]CH4_DIVOUT4 Integer Divider value
Table 10-11 Configuring LVCMOS Output Buffer(1)(2)
REGISTER BIT ADDRESSREGISTER BIT FIELD NAMEDESCRIPTION
R78[12]CH0_ENEnables OUT0 LVCMOS Buffer
R79[3:0]CH0_CMOS_SLEW_RATE_CTRLControls output slew rate of OUT0 LVCMOS Buffer
R59[14], R75[14]CH1_CMOSN_EN, CH4_CMOSP_ENEnables OUT1N/OUT4P LVCMOS Buffer
R59[13], R75[13]CH1_CMOSP_EN, CH4_CMOSN_ENEnables OUT1P/OUT4N LVCMOS Buffer
R59[12], R75[12]CH1_CMOSN_POL, CH4_CMOSP_POLSets output polarity of OUT1N/OUT4P LVCMOS Buffer
R59[11], R75[11]CH1_CMOSP_POL, CH4_CMOSN_POLSets output polarity of OUT1P/OUT4N LVCMOS Buffer
R60[3:0], R76[3:0]CH1_CMOS_SLEW_RATE_CTRL, CH4_CMOS_SLEW_RATE_CTRLControls output slew rate of OUT1/OUT4 LVCMOS Buffer
(1) Multiple output buffers should not be enabled at the same time
(2) Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8 V, safety_1p8v_mode should be set.
Table 10-12 Configuring LP-HCSL Output Buffer(1)(2)(3)
REGISTER BIT ADDRESSREGISTER BIT FIELD NAMEDESCRIPTION
R57[14] , R63[13], R68[13], R73[13]CH1_HCSL_EN, CH2_HCSL_EN, CH3_HCSL_EN, CH4_HCSL_ENEnables LP-HCSL buffer on OUT1/OUT2/OUT3/OUT4
(1) Multiple output buffers should not be enabled at the same time
(2) External termination not needed. Voltage mode driver.
(3) Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8 V, safety_1p8v_mode should be set.
Table 10-13 Configuring LVDS-Like Output Buffer(1)(2)(3)
REGISTER BIT ADDRESSREGISTER BIT FIELD NAMEDESCRIPTION
R59[15], R65[11], R70[11], R75[15]CH1_LVDS_EN, CH2_LVDS_EN, CH3_LVDS_EN, CH4_LVDS_ENEnables LVDS-like buffer on OUT1/OUT2/OUT3/OUT4
R60[15:12], R66[3:0], R71[3:0], R76[9:6]CH1_DIFFBUF_IBIAS_TRIM, CH2_DIFFBUF_IBIAS_TRIM, CH3_DIFFBUF_IBIAS_TRIM, CH4_DIFFBUF_IBIAS_TRIMSets the output swing and output common mode of OUT1/OUT2/OUT3/OUT4
R60[11:10], R66[5:4], R71[5:4], R76[5:4]CH1_LVDS_CMTRIM_INC, CH2_LVDS_CMTRIM_INC, CH3_LVDS_CMTRIM_INC, CH4_LVDS_CMTRIM_INCIncreases the output common mode of OUT1/OUT2/OUT3/OUT4. 2.5 V/3.3 V mode only.
R60[5:4], R65[14:13], R71[10:9], R77[1:0]CH1_LVDS_CMTRIM_DEC, CH2_LVDS_CMTRIM_DEC, CH3_LVDS_CMTRIM_DEC, CH4_LVDS_CMTRIM_DECDecreases the output common mode of OUT1/OUT2/OUT3/OUT4. For 2.5-V or 3.3-V mode only.
(1) Multiple output buffers should not be enabled at the same time.
(2) 100 Ω differential termination needed in DC-coupled mode. A 50-Ω, single-ended or 100-Ω differential termination is needed in AC-coupled mode
(3) Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8 V, safety_1p8v_mode should be set.