SNAS705D January   2017  – February 2024 CDCE813-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 I2C Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA and SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 I2C Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Revision History

Changes from Revision C (April 2019) to Revision D (February 2024)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed all instances of legacy terminology to controller and target where I2C is mentionedGo
  • Changed the Device Information table Package Information Go
  • Added information on allowable data inputs during the EEPROM write cycle in Data Protocol Go

Changes from Revision B (May 2018) to Revision C (April 2019)

  • Added CDCE813R02-Q1 orderable information to the data sheetGo
  • Added Device Comparison table Go
  • Added default configuration information to the S0 pin descriptionGo
  • Removed 'CDCE813-Q1' text from the VDDOUT pin description. The information applies to both CDCE813-Q1 and CDCE813R02-Q1 orderablesGo
  • Added S0 pin information in the Overview sectionGo
  • Added S0 pin information to the Default Device Configuration sectionGo
  • Added CDCE813R02-Q1 Default Configuration graphicGo
  • Changed S0 pin information in the Factory Default Setting for Control Terminal Register tablenoteGo
  • Added Y1_ST1 default settings for the CDCE813-Q1 and CDCE813R02-Q1 orderablesGo
  • Added Y1_1 default settings for the CDCE813-Q1 and CDCE813R02-Q1 orderablesGo

Changes from Revision A (May 2018) to Revision B (May 2018)

  • Changed the text in the Default Device Configuration section from: However the outputs are disabled by default and need to be turned on through I2C or with the S0 pin to: However the outputs are disabled by default and need to be turned on through I2CGo
  • Changed the Factory Default Setting table and Default Configuration graphic text to show that the Y1 outputs as 3-state when S0 = 1 or S0 = 0Go
  • Changed the default value of the TARGET 1:0 bits from: 00b to: 01b in the Generic Configuration Register tableGo
  • Changed the default value of the Y1_ST0 3:2 bits from: 11b to: 01b in the Generic Configuration Register tableGo
  • Changed the default value of the BCOUNT 7:1 bits from: 20h to: 00h in the Generic Configuration Register tableGo
  • Changed the default value of the Y2Y3_1 bit from: 1b to: 0b in the PLL1 Configuration Register tableGo

Changes from Revision * (January 2017) to Revision A (May 2018)

  • Changed the Factory Default Setting table and Default Configuration graphic text to show that S0 = 1 means Y1 outputs 3-state and S0 = 0 means Y1 is enabledGo