SNAS705D January   2017  – February 2024 CDCE813-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 I2C Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA and SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 I2C Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1 Overview

The CDCExxx-Q1 devices are modular PLL-based, low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to three output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated configurable PLL.

The CDCExxx-Q1 devices have separate output supply pins, VDDOUT, with output of 2.5 V to 3.3 V.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF. Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control signal, that is, the PWM signal.

The deep M / N divider ratio allows the generation of zero-ppm audio-video, networking (WLAN, Bluetooth, Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input frequency.

The PLL supports spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristics.

The device supports nonvolatile EEPROM programming for easy customization of the device to the application. The device is preset to a factory default configuration (see Default Device Configuration) that can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA-SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC setting for lowering EMI, or control other features like outputs disable to low, outputs in Hi-Z state, power down, PLL bypass, and so forth). For CDCE813-Q1, the S0 pin is unused by default. For the CDCE813R02-Q1, the S0 control input pin provides output enable (OE) control for output Y1 only.

The CDCE813-Q1 core operates in a 1.8-V environment. It operates in a temperature range of –40°C to 105°C.