SNAS705 Data sheet

SNAS705D January 2017 – February 2024 CDCE813-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PW|14
- MPDS360A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
OVERALL PARAMETER
I_DD	Supply current (see Figure 5-1)	All outputs off, f_CLK = 27 MHz, f_VCO = 135 MHz, f_OUT = 27 MHz	All PLLS on		11		mA
I_DD	Supply current (see Figure 5-1)		Per PLL		9		mA
I_DD(OUT)	Supply current (see Figure 5-2 )	No load, all outputs on, f_OUT = 27 MHz	V_DDOUT = 3.3 V		1.3		mA
I_DD(PD)	Power-down current. Every circuit powered down except I²C	f_IN = 0 MHz, V_DD = 1.9 V			30		μA
V_(PUC)	Supply voltage V_DD threshold for power-up control circuit			0.85		1.45	V
f_VCO	VCO frequency range of PLL			70		230	MHz
f_OUT	LVCMOS output frequency	V_DDOUT = 3.3 V				230	MHz
LVCMOS PARAMETER
V_IK	LVCMOS input voltage	V_DD = 1.7 V, I_I = –18 mA				–1.2	V
I_I	LVCMOS input current	V_I = 0 V or V_DD, V_DD = 1.9 V				±5	μA
I_IH	LVCMOS input current for S0, S1, and S2	V_I = V_DD, V_DD = 1.9 V				5	μA
I_IL	LVCMOS input current for S0, S1, and S2	V_I = 0 V, V_DD = 1.9 V				–4	μA
C_I	Input capacitance at Xin/CLK	V_IClk = 0 V or V_DD			6		pF
	Input capacitance at Xout	V_IXout = 0 V or V_DD			2
	Input capacitance at S0, S1, and S2	V_IS = 0 V or V_DD			3
CDCE813-Q1, LVCMOS PARAMETER FOR V_DDOUT = 3.3-V MODE
V_OH	LVCMOS high-level output voltage	V_DDOUT = 3 V, I_OH = –0.1 mA		2.9			V
		V_DDOUT = 3 V, I_OH = –8 mA		2.4
		V_DDOUT = 3 V, I_OH = –12 mA		2.2
V_OL	LVCMOS low-level output voltage	V_DDOUT = 3 V, I_OL = 0.1 mA				0.1	V
		V_DDOUT = 3 V, I_OL = 8 mA				0.5
		V_DDOUT = 3 V, I_OL = 12 mA				0.8
t_PLH, t_PHL	Propagation delay	PLL bypass			3.2		ns
t_PLH, t_PHL	Propagation delay	PLL enabled (f_CLK = f_VCO), 70 MHz ≤ f_VCO ≤ 85 MHz		1.6		4.3	ns
t_r, t_f	Rise and fall time	V_DDOUT = 3.3 V (20%–80%)			0.6		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾	1 PLL switching, Y2-to-Y3, 10,000 cycles			50	200	ps
t_jit(per)	Peak-to-peak period jitter⁽²⁾	1 PLL switching, Y2-to-Y3			60	200	ps
t_sk(o)	Output skew (see Table 7-2)⁽³⁾	f_OUT = 50 MHz, Y1-to-Y3				440	ps
odc	Output duty cycle ⁽⁴⁾	f_VCO = 100 MHz, Pdiv = 1		45%		55%
CDCE813-Q1, LVCMOS PARAMETER FOR V_DDOUT = 2.5-V MODE
V_OH	LVCMOS high-level output voltage	V_DDOUT = 2.3 V, I_OH = –0.1 mA		2.2			V
		V_DDOUT = 2.3 V, I_OH = –6 mA		1.7
		V_DDOUT = 2.3 V, I_OH = –10 mA		1.6
V_OL	LVCMOS low-level output voltage	V_DDOUT = 2.3 V, I_OL = 0.1 mA				0.1	V
		V_DDOUT = 2.3 V, I_OL = 6 mA				0.5
		V_DDOUT = 2.3 V, I_OL = 10 mA				0.7
t_PLH, t_PHL	Propagation delay	PLL bypass			3.6		ns
t_r, t_f	Rise and fall time	V_DDOUT = 2.5 V (20%–80%)			0.8		ns
t_jit(cc)	Cycle-to-cycle jitter⁽²⁾	1 PLL switching, Y2-to-Y3, 10,000 cycles			50	200	ps
t_jit(per)	Peak-to-peak period jitter⁽²⁾	1 PLL switching, Y2-to-Y3			60	200	ps
t_sk(o)	Output skew (see Table 7-2)⁽³⁾	f_OUT = 50 MHz, Y1-to-Y3				440	ps
odc	Output duty cycle⁽⁴⁾	f_VCO = 100 MHz, Pdiv = 1		45%		55%
I²C PARAMETER
V_IK	SCL and SDA input clamp voltage	V_DD = 1.7 V, I_I = –18 mA				–1.2	V
I_IH	SCL and SDA input current	V_I = V_DD, V_DD = 1.9 V				±10	μA
V_IH	I²C input high voltage⁽⁵⁾			0.7 × V_DD			V
V_IL	I²C input low voltage⁽⁵⁾					0.3 × V_DD	V
V_OL	SDA low-level output voltage	I_OL = 3 mA, V_DD = 1.7 V				0.2 × V_DD	V
C_I	SCL-SDA input capacitance	V_I = 0 V or V_DD			3	10	pF
EEPROM SPECIFICATION
EEcyc	Programming cycles of EEPROM			100	1000		cycles
EEret	Data retention			10			years

(1) All typical values are at respective nominal V_DD.

(2) Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, f_VCO = 108 MHz, f_OUT = 27 MHz (measured at Y2).

(3) The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.

(4) odc depends on the output rise and fall time (t_r and t_f); data sampled on the rising edge (t_r)

(5) SDA and SCL pins are 3.3-V tolerant.