SLAS564H August 2007 – July 2024 CDCE937 , CDCEL937
PRODUCTION DATA
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
fCLK | LVCMOS clock input frequency | PLL bypass mode | 0 | 160 | MHz | |
PLL mode | 8 | 160 | ||||
tr / tf | Rise and fall time CLK signal (20% to 80%) | 3 | ns | |||
dutyCLK | Duty cycle CLK at VDD/2 | 40% | 60% |