SLAS564H August   2007  – July 2024 CDCE937 , CDCEL937

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: CLK_IN
    7. 5.7 Timing Requirements: SDA/SCL
    8. 5.8 EEPROM Specification
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Register Maps
    1. 8.1 SDA/SCL Configuration Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYP(1)MAXUNIT
IDDSupply current (see Figure 5-1)All outputs off, f(CLK) = 27 MHz,
f(VCO) = 135 MHz		All PLLS on29mA
Per PLL9
IDDOUTOutput supply current
(see Figure 5-2 and Figure 5-3)		No load, all outputs on,
fOUT = 27 MHz		CDCE937,
VDDOUT = 3.3 V		3.1mA
CDCEL937,
VDDOUT = 1.8 V		1.5
IDD(PD)Power-down currentEvery circuit powered down except SDA/SCL,
fIN = 0 MHz, VDD = 1.9 V		50µA
V(PUC)Supply voltage Vdd threshold for power-up control circuit0.851.45V
f(VCO)VCO frequency range of PLL80230MHz
fOUTLVCMOS output frequencyVddout = 3.3 V230MHz
Vddout = 1.8 V230
LVCMOS PARAMETER
VIKLVCMOS input voltageVDD = 1.7 V, II = –18 mA–1.2V
IILVCMOS Input currentVI = 0 V or VDD, VDD = 1.9 V±5µA
IIHLVCMOS Input current for S0/S1/S2VI = VDD, VDD = 1.9 V5µA
IILLVCMOS Input current for S0/S1/S2VI = 0 V, VDD = 1.9 V–4µA
CIInput capacitance at Xin/ClkVI(Clk) = 0 V or VDD6pF
Input capacitance at XoutVI(Xout) = 0 V or VDD2
Input capacitance at S0/S1/S2VIS = 0 V or VDD3
CDCE937 – LVCMOS FOR Vddout = 3.3 V
VOHLVCMOS high-level output voltageVddout = 3 V, IOH = –0.1 mA2.9V
Vddout = 3 V, IOH = –8 mA2.4
Vddout = 3 V, IOH = –12 mA2.2
VOLLVCMOS low-level output voltageVddout = 3 V, IOL = 0.1 mA0.1V
Vddout = 3 V, IOL = 8 mA0.5
Vddout = 3 V, IOL = 12 mA0.8
tPLH, tPHLPropagation delayAll PLL bypass3.2ns
tr/tfRise and fall timeVddout = 3.3 V (20%–80%)0.6ns
tjit(cc)Cycle-to-cycle jitter(2)(3)1 PLL switching, Y2-to-Y36090ps
3 PLL switching, Y2-to-Y7100150
tjit(per)Peak-to-peak period jitter(3)1 PLL switching, Y2-to-Y370100ps
3 PLL switching, Y2-to-Y7120180
tsk(o)Output skew(4) (see Table 7-2)fOUT = 50 MHz, Y1-to-Y360ps
fOUT = 50 MHz, Y2-to-Y5160
odcOutput duty cycle(5)fVCO = 100 MHz, Pdiv = 145%55%
CDCE937 – LVCMOS FOR Vddout = 2.5 V
VOHLVCMOS high-level output voltageVddout = 2.3 V, IOH = –0.1 mA2.2V
Vddout = 2.3 V, IOH = –6 mA1.7
Vddout = 2.3 V, IOH = –10 mA1.6
VOLLVCMOS low-level output voltageVddout = 2.3 V, IOL = 0.1 mA0.1V
Vddout = 2.3 V, IOL = 6 mA0.5
Vddout = 2.3 V, IOL = 10 mA0.7
tPLH, tPHLPropagation delayAll PLL bypass3.4ns
tr/tfRise and fall timeVddout = 2.5 V (20%–80%)0.8ns
tjit(cc)Cycle-to-cycle jitter(2)(3)1 PLL switching, Y2-to-Y36090ps
3 PLL switching, Y2-to-Y7100150
tjit(per)Peak-to-peak period jitter(4)1 PLL switching, Y2-to-Y370100ps
3 PLL switching, Y2-to-Y7120180
tsk(o)Output skew(4)
(see Table 7-2)		fOUT = 50 MHz, Y1-to-Y360ps
fOUT = 50 MHz, Y2-to-Y5160
odcOutput duty cycle(5)f(VCO) = 100 MHz, Pdiv = 145%55%
CDCEL937 – LVCMOS FOR Vddout = 1.8 V
VOHLVCMOS high-level output voltageVddout = 1.7 V, IOH = –0.1 mA1.6V
Vddout = 1.7 V, IOH = –4 mA1.4
Vddout = 1.7 V, IOH = –8 mA1.1
VOLLVCMOS low-level output voltageVddout = 1.7 V, IOL = 0.1 mA0.1V
Vddout = 1.7 V, IOL = 4 mA0.3
Vddout = 1.7 V, IOL = 8 mA0.6
tPLH, tPHLPropagation delayAll PLL bypass2.6ns
tr/tfRise and fall timeVddout= 1.8 V (20%–80%)0.7ns
tjit(cc)Cycle-to-cycle jitter(2)(3)1 PLL switching, Y2-to-Y370120ps
3 PLL switching, Y2-to-Y7100150
tjit(per)Peak-to-peak period jitter(3)1 PLL switching, Y2-to-Y390140ps
3 PLL switching, Y2-to-Y7120190
tsk(o)Output skew(4)
(see Table 7-2)		fOUT = 50 MHz, Y1-to-Y360ps
fOUT = 50 MHz, Y2-to-Y5160
odcOutput duty cycle(5)f(VCO) = 100 MHz, Pdiv = 145%55%
SDA AND SCL
VIKSCL and SDA input clamp voltageVDD = 1.7 V; II = –18 mA–1.2V
IIHSCL and SDA input currentVI = VDD; VDD = 1.9 V±10µA
VIHSDA/SCL input high voltage(6)0.7 × VDDV
VILSDA/SCL input low voltage(6)0.3 × VDDV
VOLSDA low-level output voltageIOL = 3 mA, VDD = 1.7 V0.2 × VDDV
CISCL/SDA Input capacitanceVI = 0 V or VDD310pF
(1) All typical values are at respective nominal VDD.
(2) 10000 cycles.
(3) Jitter depends on configuration. Data is taken under the following conditions: 1-PLL is fIN = 27 MHz and Y2/3 = 27 MHz (measured at Y2); 3-PLL is fIN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, and Y6/7 = 74.25 MHz.
(4) The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data taking on rising edge (tr).
(5) odc depends on output rise and fall time (tr/tf).
(6) SDA and SCL pins are 3.3-V tolerant.