SCAS945A June   2015  – September 2015 CDCEL824

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 CLK_IN Timing Requirements
    7. 7.7 SDA/SCL Timing Requirements
    8. 7.8 EEPROM Specification
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Control Pins Settings
      2. 9.3.2 SDA/SCL Serial Interface
      3. 9.3.3 SDA/SCL Hardware Interface
    4. 9.4 Device Functional Modes
      1. 9.4.1 Default Device Setting
    5. 9.5 Programming
      1. 9.5.1 Data Protocol
      2. 9.5.2 Command Code Definition
      3. 9.5.3 Generic Programming Sequence
      4. 9.5.4 Byte Write Programming Sequence
      5. 9.5.5 Byte Read Programming Sequence
      6. 9.5.6 Block Write Programming Sequence
      7. 9.5.7 Block Read Programming Sequence
    6. 9.6 Register Maps
      1. 9.6.1 SDA/SCL Configuration Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PLL Multiplier/Divider Definition
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2]: for example, Frequency Switching, Output Enable, or Power Down
    • Enables 0-PPM Clock Generation
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Settings
  • Flexible Input Clocking Concept
    • External Crystal: 20 MHz to 30 MHz
    • Single-Ended LVCMOS up to 130 MHz
  • Selectable Output Frequency up to 201 MHz
  • Low-Noise PLL Core
    • PLL Loop Filter Components Integrated
    • Low Period Jitter (Typical 80 ps)
  • 1.8-V Device Power Supply
  • Temperature Range –40°C to 85°C
  • Packaged in TSSOP

2 Applications

    Laser Distance Measurement Applications

3 Description

The CDCEL824 is a modular PLL-based low-cost, high-performance, programmable clock synthesizer, multiplier, and divider. It generates up to four output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 201 MHz, using up to two independent configurable PLLs.

The CDCEL824 has a separate output supply pins, VDDOUT, which are 1.8 V.

The input accepts an external crystal or LVCMOS clock signal. In case of a crystal input, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCEL824 TSSOP (16) 5.00 mm x 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Schematic

CDCEL824 typical_application_schematic_scas945.gif