SCAS892C February   2010  – December 2016 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Control Terminal Setting
      2. 10.3.2 Default Device Setting
    4. 10.4 Device Functional Modes
      1. 10.4.1 SDA and SCL Serial Interface
    5. 10.5 Programming
      1. 10.5.1 Data Protocol
      2. 10.5.2 Command Code Definition
      3. 10.5.3 Generic Programming Sequence
      4. 10.5.4 Byte Write Programming Sequence
      5. 10.5.5 Byte Read Programming Sequence
      6. 10.5.6 Block Write Programming Sequence
      7. 10.5.7 Block Read Programming Sequence
      8. 10.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 10.5.9 SDA and SCL Hardware Interface
    6. 10.6 Register Maps
      1. 10.6.1 SDA and SCL Configuration Registers
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Spread-Spectrum Clock (SSC)
        2. 11.2.2.2 PLL Multiplier or Divider Definition
        3. 11.2.2.3 Crystal Oscillator Start-Up
        4. 11.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 11.2.2.5 Unused Inputs and Outputs
        6. 11.2.2.6 Switching Between XO and VCXO Mode
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Setting
  • Flexible Input Clocking Concept
    • External Crystal: 8 MHz to 32 MHz
    • On-Chip VCXO: Pull Range ±150 ppm
    • Single-Ended LVCMOS up to 160 MHz
  • Free Selectable Output Frequency up to 230  MHz
  • Low-Noise PLL Core
    • Integrated PLL Loop Filter Components
    • Low Period Jitter (Typical 60 ps)
  • Separate Output Supply Pins
    • CDCE937-Q1: 3.3 V and 2.5 V
    • CDCEL937-Q1: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2]; for Example: SSC Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth™, WLAN, Ethernet™, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Power Supply
  • Wide Temperature Range –40°C to 125°C
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)

2 Applications

  • Clusters
  • Head Units
  • Navigation Systems
  • Advanced Driver Assistance Systems (ADAS)

3 Description

The CDCE937-Q1 and CDCEL937-Q1 devices are modular, phase-locked loop (PLL) based programmable clock synthesizers. These devices provide flexible and programmable options, such as output clocks, input signals, and control pins, so that the user can configure the CDCEx937-Q1 for their own specifications.

The CDCEx937-Q1 generates up to seven output clocks from a single input frequency to enable both board space and cost savings. Additionally, with multiple outputs, the clock generator can replace multiple crystals with one clock generator. This makes the device well-suited for head unit and telematics applications in infotainment and camera systems in ADAS as these platforms are evolving into smaller and more cost effective systems.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCE937-Q1,
CDCEL937-Q1		 TSSOP (20) 6.50 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Block Diagram

CDCE937-Q1 CDCEL937-Q1 app_po_cir_las564.gif