SCAS892C February   2010  – December 2016 CDCE937-Q1 , CDCEL937-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Control Terminal Setting
      2. 10.3.2 Default Device Setting
    4. 10.4 Device Functional Modes
      1. 10.4.1 SDA and SCL Serial Interface
    5. 10.5 Programming
      1. 10.5.1 Data Protocol
      2. 10.5.2 Command Code Definition
      3. 10.5.3 Generic Programming Sequence
      4. 10.5.4 Byte Write Programming Sequence
      5. 10.5.5 Byte Read Programming Sequence
      6. 10.5.6 Block Write Programming Sequence
      7. 10.5.7 Block Read Programming Sequence
      8. 10.5.8 Timing Diagram for the SDA and SCL Serial Control Interface
      9. 10.5.9 SDA and SCL Hardware Interface
    6. 10.6 Register Maps
      1. 10.6.1 SDA and SCL Configuration Registers
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Spread-Spectrum Clock (SSC)
        2. 11.2.2.2 PLL Multiplier or Divider Definition
        3. 11.2.2.3 Crystal Oscillator Start-Up
        4. 11.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 11.2.2.5 Unused Inputs and Outputs
        6. 11.2.2.6 Switching Between XO and VCXO Mode
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Related Links
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 Community Resources
    5. 14.5 Trademarks
    6. 14.6 Electrostatic Discharge Caution
    7. 14.7 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

PW Package
20-Pin TSSOP
Top View
CDCE937-Q1 CDCEL937-Q1 Pin_Diagram.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 Xin/CLK I Crystal oscillator input or LVCMOS clock input (selectable through SDA and SCL bus)
2 S0 I User-programmable control input S0; LVCMOS inputs; Internal pullup 500 k
3 VDD P 1.8-V power supply for the device
4 VCtrl I VCXO control voltage (leave open or pull up to approximately 500 k when not used)
5 GND G Ground
6 Vddout P CDCE937-Q1: 3.3-V or 2.5-V supply for all outputs
CDCEL937-Q1: 1.8-V supply for all outputs
7 Y4 O LVCMOS outputs
8 Y5 O LVCMOS outputs
9 GND G Ground
10 Vddout P CDCE937-Q1: 3.3-V or 2.5-V supply for all outputs
CDCEL937-Q1: 1.8-V supply for all outputs
11 Y7 O LVCMOS outputs
12 Y6 O LVCMOS outputs
13 Vddout P CDCE937-Q1: 3.3-V or 2.5-V supply for all outputs
CDCEL937-Q1: 1.8-V supply for all outputs
14 Y3 O LVCMOS outputs
15 Y2 O LVCMOS outputs
16 GND G Ground
17 Y1 O LVCMOS outputs
18 SCL/S2 I SCL: serial clock input(default configuration), LVCMOS internal pullup 500 k; or
S2: user-programmable control input, LVCMOS inputs, and internal pullup 500 k
19 SDA/S1 I/O or I SDA: bidirectional serial data input/output (default configuration). LVCMOS internal pullup 500 k; or
S1: user-programmable control input, LVCMOS inputs, and internal pullup 500 k
20 Xout O Crystal oscillator output (leave open or pull up to approximately 500 k when not used)
(1) G = Ground, I = Input, O = Output, P = Power