SCAS844G
August 2007 – January 2024
CDCE949
,
CDCEL949
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
EEPROM Specification
5.7
Timing Requirements: CLK_IN
5.8
Timing Requirements: SDA/SCL
5.9
Typical Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Control Terminal Setting
7.3.2
Default Device Setting
7.3.3
SDA/SCL Serial Interface
7.3.4
Data Protocol
7.4
Device Functional Modes
7.4.1
SDA/SCL Hardware Interface
7.5
Programming
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Spread Spectrum Clock (SSC)
8.2.2.2
PLL Frequency Planning
8.2.2.3
Crystal Oscillator Start-Up
8.2.2.4
Frequency Adjustment With Crystal Oscillator Pulling
8.2.2.5
Unused Inputs and Outputs
8.2.2.6
Switching Between XO and VCXO Mode
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Register Maps
9.1
SDA/SCL Configuration Registers
10
Device and Documentation Support
10.1
Device Support
10.1.1
Development Support
10.2
Related Documentation
10.3
Related Links
10.4
Receiving Notification of Documentation Updates
10.5
Support Resources
10.6
Trademarks
10.7
Electrostatic Discharge Caution
10.8
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
PW|24
MPDS363A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
scas844g_oa
scas844g_pm
8.2.2
Detailed Design Procedure