SCAS844G August   2007  – January 2024 CDCE949 , CDCEL949

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Setting
      2. 7.3.2 Default Device Setting
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-Up
        4. 8.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs and Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Related Documentation
    3. 10.3 Related Links
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Control Terminal Setting

The CDCEx949 has three user-definable control terminals (S0, S1, and S2) which allow external control of device settings. They can be programmed to any of the following setting:

  • Spread spectrum clocking selection → spread type and spread amount selection
  • Frequency selection → switching between any of two user-defined frequencies
  • Output state selection → output configuration and power down control

The user can predefine up to eight different control settings. Table 7-1 and Table 7-2 explain these settings.

Table 7-1 Control Terminal Definition
EXTERNAL CONTROL BITSPLL1 SETTINGPLL2 SETTINGPLL3 SETTINGPLL4 SETTINGY1 SETTING
Control FunctionPLL Frequency SelectionSSC SelectionOutput Y2/Y3 SelectionPLL Frequency SelectionSSC SelectionOutput Y4/Y5 SelectionPLL Frequency SelectionSSC SelectionOutput Y6/Y7 SelectionPLL Frequency SelectionSSC SelectionOutput Y8/Y9 SelectionOutput Y1 and Power Down Selection
Table 7-2 PLLx Setting (Can Be Selected for Each PLL Individual)
SSC SELECTION (CENTER/DOWN)(1)
SSCx [3-bits]CENTERDOWN
0000% (off)0% (off)
001±0.25%–0.25%
010±0.5%–0.5%
011±0.75%–0.75%
100±1%–1%
101±1.25%–1.25%
110±1.5%–1.5%
111±2%–2%
FREQUENCY SELECTION(2)
FSxFUNCTION
0Frequency0
1Frequency1
OUTPUT SELECTION(3) (Y2 ... Y9)
YxYxFUNCTION
0State0
1State1
(1) Center/Down-Spread, Frequency0/1 and State0/1 are user-definable in PLLx Configuration Register
(2) Frequency0 and Frequency1 can be any frequency within the specified fVCO range
(3) State0/1 selection is valid for both outputs of the corresponding PLL module and can be power down, 3-state, low, or active
Table 7-3 Y1 Setting(1)
Y1 SELECTION
Y1FUNCTION
0State 0
1State 1
(1) State0 and State1 are user definable in Generic Configuration Register and can be power down, 3-state, low, or active.

S1/SDA and S2/SCL pins of the CDCEx949 are dual function pins. In default configuration they are defined as SDA/SCL for the serial interface. They can be programmed as control-pins (S1/S2) by setting the relevant bits in the EEPROM. Note that the changes to the Control register (Bit [6] of Byte [02]) have no effect until they are written into the EEPROM.

Once they are set as control pins, the serial programming interface is no longer available. However, if VDDOUT is forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).

S0 is not a multi-use pin and is a control pin only.