SNAS734F July 2017 – January 2024 CDCI6214
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The CDCI6214 ultra-low power clock generator provides an I2C-compatible serial interface for register and EEPROM access. The device is compatible to standard-mode I2C at 100 kHz and the fast-mode I2C at 400-kHz clock frequency.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|
Target Address A[6:0](1) | R/W# Bit(2) |
Table 8-12 shows the target address decoding with respect to EEPROMSEL pin. This enables the user to avoid in-system conflicts with different configurations, as the selected EEPROM page can be reflected in the target address least significant bit A0. Moreover a device being powered up in the silicon default, can always be expected under the default address of 0xE9 for reads (or 0xE8 for writes).
A6 | A5 | A4 | A3 | A2 | A1 | A0 | EEPROMSEL | DESCRIPTION |
---|---|---|---|---|---|---|---|---|
1 | 1 | 1 | 0 | 1 | 0 | 0 | MID | Device Default |
1 | I2C_A0(1) | LOW | EEPROM, Page 0 | |||||
1 | I2C_A0(2) | HIGH | EEPROM, Page 1 |
The serial interface uses the following protocol as shown in Figure 8-11. The target address is followed by a word-wide register offset and a word-wide register value.