SNAS734F July 2017 – January 2024 CDCI6214
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The CDCI6214 contains a fully integrated phase-locked loop circuit. The error between a reference phase and an internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes an internal voltage-controlled oscillator (VCO). The frequency of the VCO is fed through a pre-scaler feedback divider (PSFB) and another feedback divider back to the PFD.
The PLL closed-loop bandwidth is configurable using registers PLL0, PLL1, and PLL2.
fVCO in MHz(1) | fPFD in MHz | BW in MHz | Phase Margin in ° | Damping Factor | ICP in mA | CPcap IN pF | RRes IN kΩ | CZcap IN pF |
---|---|---|---|---|---|---|---|---|
pll_cp_up(2) | pll_lf_pcap | pll_lf_res | pll_lf_zcap | |||||
2400 | 25 | 0.51 | 67 | 0.9 | 2.0 | 17.5 | 2.5 | 450 |
2400 | 50 | 0.97 | 67 | 1.3 | 2.0 | 17.5 | 2.5 | 450 |
2400 | 100 | 1.41 | 68 | 1.2 | 2.4 | 17.5 | 1.5 | 450 |
2457.6 | 61.44 | 1.04 | 67 | 1.4 | 1.8 | 17.5 | 2.5 | 450 |
2500 | 25 | 0.49 | 67 | 0.9 | 2.0 | 17.5 | 2.5 | 450 |
2500 | 50 | 0.93 | 68 | 1.3 | 2.0 | 17.5 | 2.5 | 450 |
2680 | 67 | 0.38 | 67 | 1.3 | 0.2 | 19.5 | 5.5 | 480 |
2688 | 48 | 0.93 | 68 | 1.3 | 1.5 | 17.5 | 2.5 | 480 |
2688 | 96 | 0.36 | 67 | 1.0 | 0.2 | 19.5 | 3.5 | 480 |
2800 | 50 | 1.00 | 68 | 1.0 | 2.6 | 17.5 | 1.5 | 450 |
2800 | 100 | 1.00 | 68 | 1.0 | 1.3 | 17.5 | 1.5 | 450 |