SLLSEL1 November   2014 CDCL1810A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Device Comparison Tables
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 DC Electrical Characteristics
    6. 8.6 AC Electrical Characteristics
    7. 8.7 AC Electrical Characteristics for the SDA/SCL Interface
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable/Disable
      2. 9.3.2 SDA/SCL Interface
        1. 9.3.2.1 SDA/SCL Bus Slave Device Address
        2. 9.3.2.2 SDA/SCL Connections Recommendations
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SDA/SCL Interface
      2. 9.5.2 Command Code Definition
      3. 9.5.3 SDA/SCL Timing Characteristics
      4. 9.5.4 SDA/SCL Programming Sequence
    6. 9.6 Register Maps
      1. 9.6.1 SDA/SCL Bus Configuration Command Bitmap
        1. 9.6.1.1 Byte 0:
        2. 9.6.1.2 Byte 1:
        3. 9.6.1.3 Byte 2:
        4. 9.6.1.4 Byte 3:
        5. 9.6.1.5 Byte 4:
        6. 9.6.1.6 Byte 5:
        7. 9.6.1.7 Byte 6:
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Distribution for Multiple TI Keystone DSPs
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  15. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Single 1.8 V Supply
  • High-Performance Clock Distributor with 10 Outputs
  • Low Input-to-Output Additive Jitter: as low as 10fs RMS
  • Low-Voltage Differential Signaling (LVDS) Input, 100Ω Differential On-Chip Termination, up to 650 MHz Frequency
  • Differential Current Mode Logic (CML) Outputs, 50Ω Single-Ended On-Chip Termination, up to 650 MHz Frequency
  • Two Groups of Five Outputs Each with Independent Frequency Division Ratios
  • Output Frequency Derived with Divide Ratios of 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, and 80
  • Meets ANSI TIA/EIA-644-A-2001 LVDS Standard Requirements
  • Power Consumption: 410 mW Typical
  • Output Enable Control for Each Output
  • SDA/SCL Device Management Interface
  • 48-pin VQFN (RGZ) Package
  • Industrial Temperature Range: –40°C to +85°C

2 Applications

  • Clock Distribution for High-Speed SERDES
  • Distribution of SERDES Reference Clocks for 1G/10G Ethernet, 1X/2X/4X/10X Fibre Channel, PCI Express, Serial ATA, SONET, CPRI, OBSAI, and so forth
  • Up to 1-to-10 Clock Buffering and Fan-out

3 Description

The CDCL1810A is a high-performance clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency: FOUT = FIN/P, where P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80.

The CDCL1810A supports one differential LVDS clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDS receivers if they are ac-coupled.

With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810A can support a single-ended clock input as outlined in Pin Configuration and Functions.

All device settings are programmable through the SDA/SCL, serial two-wire interface. The serial interface is 1.8V tolerant only.

The device operates in a 1.8V supply environment and is characterized for operation from –40°C to +85°C. The CDCL1810A is available in a 48-pin QFN (RGZ) package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCL1810A VQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

bd_01_lls781.gif