High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when the jitter and phase noise is critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low impedance path for high-frequency noise and guards the power supply system against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed very close to the power-supply terminals and laid out with short loops to minimize inductance. TI recommends adding as many high-frequency (for example, 0.1 µF) bypass capacitors, as there are supply terminals in the package. TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock buffer; these beads prevent the switching noise from leaking into the board supply. It is imperative to choose an appropriate ferrite bead with very low DC resistance to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper operation.

Figure 13 shows this recommended power supply decoupling method.

10.1 Power Considerations

The following power consideration refers to the device-consumed power consumption only. The device power consumption is the sum of static power and dynamic power. The dynamic power usage consists of two components:

• Power used by the device as it switches states.
• Power required to charge any output load.

The output load can be capacitive only or capacitive and resistive. The following formula and the power graphs in and Figure 1 can be used to obtain the power consumption of the device:

P_dev = P_stat + n (P_dyn + P_Cload)
P_stat = V_DD × I_DD
P_dyn + P_Cload = see and Figure 1

where:

V_DD = Supply voltage ( or 2.5 V)
I_DD = Static device current (typical 6 mA for V_DD = 3.3 V; typical 3 mA for V_DD = 2.5 V)
n = Number of switching output pins

Example for device power consumption for CDCLVC1104: four outputs are switching, f = 120 MHz, V_DD = 3.3 V, and C_load = 2 pF per output:

P_dev = P_stat + n (P_dyn + P_Cload) = 19.8 mW + 40 mW = 59.8 mW
P_stat = V_DD × I_DD = 6 mA × 3.3 V = 19.8 mW
n (P_dyn + P_Cload) = 4 × 10 mW = 40 mW