SCAS946A November   2016  – January 2017 CDCLVP111-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 LVECL DC Electrical Characteristics
    6. 6.6 LVPECL DC Electrical Characteristics
    7. 6.7 AC Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Fanout Buffer for Line Card Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 LVPECL Output Termination
          2. 8.2.1.2.2 Input Termination
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Filtering
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HFG|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

HFG Package
36-Pin CFP
Top View

Pin Functions(1)

PIN TYPE DESCRIPTION
NAME NO.
CLK_SEL 2 Input Clock select. Used to select between CLK0 and CLK1 input pairs. LVTTL/LVCMOS functionality compatible.
CLK0, CLK0 3, 4 Input Differential LVECL/LVPECL input pair.
CLK1, CLK1 6, 7 Input
Q[9:0] 12, 14, 16, 20, 22, 24, 26, 30, 32, 34 Output LVECL/LVPECL clock outputs, these outputs provide low-skew copies of CLKn.
Q[9:0] 11, 13, 15, 19, 21, 23, 25, 29, 31, 33 Output LVECL/LVPECL complementary clock outputs, these outputs provide copies of CLKn.
VBB 5 Power Reference voltage output for single-ended input operation.
VCC 1, 9, 10, 17, 18, 27, 28, 35, 36 Power Supply voltage.
VEE 8 Power Device ground or negative supply voltage in ECL mode.
(1) CLKn, CLK_SEL pull down resistor = 75 kΩ; CLKn pull up resistor = 37.5 kΩ; CLKn pull down resistor = 50 kΩ.