The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP2102 clock buffer distributes two clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP2102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP2102 is characterized for operation from –40°C to +85°C and is available in a 3-mm × 3-mm, VQFN-16 package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
CDCLVP2102 | VQFN (16) | 3.00 mm × 3.00 mm |
Changes from B Revision (August 2011) to C Revision
Changes from A Revision (October 2009) to B Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage(2) | –0.5 | 4.6 | V |
VIN | Input voltage(3) | –0.5 | VCC + 0.5 | V |
VOUT | Output voltage(3) | –0.5 | VCC + 0.5 | V |
IIN | Input current | 20 | mA | |
IOUT | Output current | 50 | mA | |
TA | Specified free-air temperature (no airflow) | –40 | 85 | °C |
TJ | Maximum junction temperature | 125 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | 2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | 1500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply voltage | 2.375 | 2.5/3.3 | 3.60 | V | |
TA | Ambient temperature | –40 | 85 | °C | ||
TPCB | PCB temperature (measured at thermal pad) | 105 | °C |
THERMAL METRIC(1)(2)(3) | CDCLVP2102 | UNIT | ||
---|---|---|---|---|
RGT (VQFN) | ||||
16 PINS | ||||
RθJA | Junction-to-ambient thermal resistance (0 LFM) | 51.8(4) | °C/W | |
RθJC(top) | Junction-to-case (top) thermal resistance | 79 | °C/W | |
RθJP(5) | Junction-to-pad thermal resistance | 6.12(4) | °C/W | |
ψJT | Junction-to-top characterization parameter | 1.4 | °C/W | |
ψJB | Junction-to-board characterization parameter | 19 | °C/W | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.12 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
fIN | Input frequency | Clock input | 2000 | MHz | ||
VIN, DIFF, PP | Differential input peak-peak voltage | fIN ≤ 1.5 GHz | 0.1 | 1.5 | V | |
1.5 GHz ≤ fIN ≤ 2 GHz | 0.2 | 1.5 | V | |||
VICM | Input common-mode level | 1 | VCC – 0.3 | V | ||
IIH | Input high current | VCC = 3.6 V, VIH = 3.6 V | 40 | μA | ||
IIL | Input low current | VCC = 3.6 V, VIL = 0 V | –40 | μA | ||
ΔV/ΔT | Input edge rate | 20% to 80% | 1.5 | V/ns | ||
ICAP | Input capacitance | 5 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VOH | Output high voltage | TA = –40°C to 85°C | VCC – 1.26 | VCC – 0.9 | V | |
TPCB ≤ 105°C | VCC – 1.26 | = | VCC – 0.83 | |||
VOL | Output low voltage | TA = –40°C to 85°C | VCC – 1.7 | VCC – 1.3 | V | |
TPCB ≤ 105°C | VCC – 1.7 | VCC – 1.25 | ||||
VOUT, DIFF, PP | Differential output peak-peak voltage | fIN ≤ 2 GHz | 0.5 | 1.35 | V | |
VAC_REF | Input bias voltage(2) | IAC_REF = 2 mA | VCC – 1.6 | VCC – 1.1 | V | |
IEE | Supply internal current | Outputs unterminated, TA ≤ 85°C |
48 | mA | ||
Outputs unterminated, TPCB ≤ 105°C |
49 | |||||
ICC | Output and internal supply current | All outputs terminated, 50 Ω to VCC – 2 TA ≤ 85°C |
173 | mA | ||
All outputs terminated, 50 Ω to VCC – 2 TPCB ≤ 105°C |
189 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tPD | Propagation delay | VIN, DIFF, PP = 0.1 V | 450 | ps | ||
VIN, DIFF, PP = 0.3 V | 450 | |||||
tSK,PP | Part-to-part skew | 100 | ps | |||
tSK,O_WB | Within bank output skew | 10 | ps | |||
tSK,O_BB | Bank-to-bank output skew | Both inputs have equal skew | 15 | ps | ||
tSK,P | Pulse skew (with 50% duty cycle input) | Crossing-point-to-crossing-point distortion, fOUT = 100 MHz | –50 | 50 | ps | |
tRJIT | Random additive jitter (with 50% duty cycle input) | fOUT = 100 MHz, VIN,SE = VCC, Vth = 1.25 V, 10 kHz to 20 MHz |
0.089 | ps, RMS | ||
fOUT = 100 MHz, VIN,SE = 0.9 V, Vth = 1.1 V, 10 kHz to 20 MHz |
0.093 | ps, RMS | ||||
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz |
0.037 | ps, RMS | ||||
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V, VICM = 1 V, 10 kHz to 20 MHz |
0.094 | ps, RMS | ||||
fOUT = 100 MHz, VIN,DIFF,PP = 1 V, VICM = 1 V, 10 kHz to 20 MHz |
0.091 | ps, RMS | ||||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 |
–52.5 | dBc | ||||
PSPUR | Coupling on differential OUT8 from OUT7 in the frequency spectrum of fOUT, 8 ±(fOUT, 8/2) with synchronous inputs |
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V |
–66.8 | dBc | ||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 |
–52 | |||||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V |
–66.4 | |||||
tR/tF | Output rise/fall time | 20% to 80% | 200 | ps |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tPD | Propagation delay | VIN, DIFF, PP = 0.1 V | 450 | ps | ||
VIN, DIFF, PP = 0.3 V | 450 | |||||
tSK,PP | Part-to-part skew | 100 | ps | |||
tSK,O_WB | Within bank output skew | 10 | ps | |||
tSK,O_BB | Bank-to-bank output skew | Both inputs have equal skew | 15 | ps | ||
tSK,P | Pulse skew (with 50% duty cycle input) | Crossing-point-to-crossing-point distortion, fOUT = 100 MHz | –50 | 50 | ps | |
tRJIT | Random additive jitter (with 50% duty cycle input) | fOUT = 100 MHz,(2) VIN,SE = VCC, Vth = 1.65 V, 10 kHz to 20 MHz |
0.081 | ps, RMS | ||
fOUT = 100 MHz,(2) VIN,SE = 0.9 V, Vth = 1.1 V, 10 kHz to 20 MHz |
0.097 | ps, RMS | ||||
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz |
0.05 | ps, RMS | ||||
fOUT = 100 MHz,(2) VIN,DIFF,PP = 0.15 V, VICM = 1 V, 10 kHz to 20 MHz |
0.098 | ps, RMS | ||||
fOUT = 100 MHz,(2) VIN,DIFF,PP = 1 V, VICM = 1 V, 10 kHz to 20 MHz |
0.095 | ps, RMS | ||||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 |
–55.3 | dBc | ||||
fOUT = 100 MHz(3), Input AC-coupled, VICM = VAC_REF, 12 kHz to 20 MHz |
0.068 | ps, RMS | ||||
fOUT = 122.88 MHz(4), Input AC-coupled, VICM = VAC_REF, 12 kHz to 20 MHz |
0.056 | ps, RMS | ||||
fOUT = 156.25 MHz(5), Input AC-coupled, VICM = VAC_REF, 12 kHz to 20 MHz |
0.047 | ps, RMS | ||||
fOUT = 312.5 MHz(6), Input AC-coupled, VICM = VAC_REF, 12 kHz to 20 MHz |
0.026 | ps, RMS | ||||
PSPUR | Coupling on differential OUT8 from OUT7 in the frequency spectrum of fOUT, 8 ±(fOUT, 8/2) with synchronous inputs |
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 62.5 MHz, VIN,SIFF,PP,1 = 1 V, VICM, 1 = 1 V |
–65.1 | dBc | ||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,SE,1 = VCC, Vth, 1 = VCC/2 |
–54.7 | |||||
fOUT,8 = 500 MHz, VIN,DIFF,PP,0 = 0.15 V, VICM, 0 = 1 V, fOUT, 7 = 15.625 MHz, VIN,DIFF,PP,1 = 1 V, VICM, 1 = 1 V |
–66.7 | |||||
tR/tF | Output rise/fall time | 20% to 80% | 200 | ps |
Figure 1 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 2.
Figure 5 through Figure 11 show how the device should be set up for a variety of test configurations.