11.1 Layout Guidelines

Power consumption of the CDCLVP2102 can be high enough to require attention to thermal management. For reliability and performance reasons, the die temperature must be limited to a maximum of 125°C. That is, as an estimate, ambient temperature (T_A) plus device power consumption times R_θJA must not exceed 125°C.

The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. Figure 24 shows a recommended land and via pattern.

11.2 Layout Example

Figure 24. Recommended PCB Layout

11.3 Thermal Considerations

The CDCLVP2102 supports high temperatures on the printed circuit board (PCB) measured at the thermal pad. The system designer must ensure that the maximum junction temperature is not exceeded. Ψ_JB can allow the system designer to measure the board temperature with a fine gauge thermocouple and back calculate the junction temperature using Equation 1. Note that Ψ_jb is close to R_θJB because 75 to 95% of the heat of a device is dissipated by the PCB. Further information can be found at SPRA953 and SLUA566.

Example:

Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:

T_PCB = 105°C

Ψ_JB = 19°C/W

Power_inclTerm = I_max × V_max = 189 mA × 3.6 V = 680 mW (maximum power consumption including termination resistors)

Power_exclTerm = 529 mW (maximum power consumption excluding termination resistors, see SLYT127 for further details)

ΔT_junction = Ψ_JB × Power_exclTerm = 19°C/W × 529 mW = 10.06°C

T_junction = ΔT_junction + T_Chassis = 10.06°C + 105°C = 115°C (the maximum junction temperature of 125°C is not violated)