SCAS759C April   2004  – July 2017 CDCM1802

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics
    7. 6.7  Jitter Characteristics
    8. 6.8  Supply Current Electrical Characteristics
    9. 6.9  Control Input Characteristics
    10. 6.10 Timing Requirements
    11. 6.11 Bias Voltage VBB
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Control Pin Settings
      2. 8.4.2 Device Behavior During RESET and Control Pin Switching
        1. 8.4.2.1 Output Behavior When Enabling the Device (EN = 0 → 1)
        2. 8.4.2.2 Enabling a Single Output Stage
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 LVPECL Receiver Input Termination
      2. 9.1.2 LVCMOS Receiver Input Termination
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 LVPECL Receiver Input Termination

The input of the CDCM1802 has high impedance and comes with a very large common mode voltage range. For optimized noise performance it is recommended to properly terminate the PCB trace (transmission line).

Additional termination techniques can be found in the following application notes: SCAA062 and SCAA059.

CDCM1802 LVPECL_IN-TERM.gif Figure 15. Recommended AC-Coupling LVPECL Receiver Input Termination
CDCM1802 LVPECL_IN-TERM_DC.gif Figure 16. Recommended DC-Coupling LVPECL Receiver Input Termination

9.1.2 LVCMOS Receiver Input Termination

CDCM1802 LVCMOS_IN-TERM.gif

NOTE:

CAC − AC-coupling capacitor (for example, 10 nF)
CCT − Capacitor keeps voltage at IN constant (for example, 10 nF)
Rdc − Load and correct duty cycle (for example, 50 Ω)
VBB − Bias voltage output
Figure 17. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1802

9.2 Typical Application

Figure 18 shows a fanout buffer application.

CDCM1802 typical_application_1802.gif Figure 18. Typical Application Schematic, CDCM1802

9.2.1 Design Requirements

The CDCM1802 shown in Figure 18 is configured to be able to select an 100-MHz LVPECL clock from the backplane. The signal can be fanned out to desired devices, as shown. The CDCM1802 offers internal dividers for both the LVCMOS and LVPECL output. In the example the LVCMOS output is divided by 4 and the LVPECL output is divided by 1.

  • The PHY device receive a single ended 25-MHz signal. Optionally a series resistance can be placed close to the output to match transmission line impedance and reduce reflections.
  • The ASIC is capable of DC coupling with a 3.3-V LVPECL driver such as the CDCM1802. This ASIC features internal termination so no additional components are needed.
  • S0, S1, EN needs to be set accordingly to ensure the required divider setting.

9.2.2 Detailed Design Procedure

Refer to LVPECL Receiver Input Termination for proper input terminations, dependent on single-ended or differential inputs.

Refer to Figure 9 and Figure 10 for output termination schemes depending on the receiver application.

Refer to Table 1 for setting the desired divider modes.

9.2.3 Application Curve

CDCM1802 appcurve_125MHz_SCAS759B.jpg
Input (Vectron C5310A1) = 83 fs, rms Output (LVPECL, divide 1) = 134 fs, rms
additive jitter = 105 fs, rms (typ)
Figure 19. Additive Jitter Performance