SCAS759C April   2004  – July 2017 CDCM1802

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics
    7. 6.7  Jitter Characteristics
    8. 6.8  Supply Current Electrical Characteristics
    9. 6.9  Control Input Characteristics
    10. 6.10 Timing Requirements
    11. 6.11 Bias Voltage VBB
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Control Pin Settings
      2. 8.4.2 Device Behavior During RESET and Control Pin Switching
        1. 8.4.2.1 Output Behavior When Enabling the Device (EN = 0 → 1)
        2. 8.4.2.2 Enabling a Single Output Stage
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 LVPECL Receiver Input Termination
      2. 9.1.2 LVCMOS Receiver Input Termination
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

TI recommends taking special care of the PCB design for good thermal flow from the VQFN 16-pin package to the PCB. The current consumption of the CDCM1802 is fixed. JEDEC JESD51−7 specifies thermal conductivity for standard PCB boards.

To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications.

See the SCBA017 and the SLUA271 application notes for further package-related information.

11.2 Layout Example

CDCM1802 m0029-01.gif Figure 21. Recommended Thermal Via Placement

11.3 Thermal Considerations

Table 2. Package Thermal Resistance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RθJA VQFN−16 package thermal resistance with thermal vias in PCB(1) 4-layer JEDEC test board (JESD51−7) with four thermal vias of 22-mil diameter each, airflow = 0 ft/min 48.4 °C/W
(1) It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good heat sink.
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TChassis = 85°C (temperature of the chassis)
Peffective = Imax × Vmax = 85 mA × 3.6 V = 306 mW (max power consumption inside the package)
ΔTJunction = RθJA × Peffective = 40.8°C/W × 306 mW = 12.48°C
TJunction = ΔTJunction + TChassis = 12.48°C + 85°C = 97.48°C (the maximum junction temperature of Tdie−max = 125°C is not violated)