SCAS931G May   2012  – January 2018 CDCM6208

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information, Airflow = 0 LFM
    5. 6.5  Thermal Information, Airflow = 150 LFM
    6. 6.6  Thermal Information, Airflow = 250 LFM
    7. 6.7  Thermal Information, Airflow = 500 LFM
    8. 6.8  Single-Ended Input Characteristics (SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, SYNCN, REF_SEL)
    9. 6.9  Single-Ended Input Characteristics (PRI_REF, SEC_REF)
    10. 6.10 Differential Input Characteristics (PRI_REF, SEC_REF)
    11. 6.11 Crystal Input Characteristics (SEC_REF)
    12. 6.12 Single-Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)
    13. 6.13 PLL Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 LVPECL (High-Swing CML) Output Characteristics
    16. 6.16 CML Output Characteristics
    17. 6.17 LVDS (Low-Power CML) Output Characteristics
    18. 6.18 HCSL Output Characteristics
    19. 6.19 Output Skew and Sync to Output Propagation Delay Characteristics
    20. 6.20 Device Individual Block Current Consumption
    21. 6.21 Worst Case Current Consumption
    22. 6.22 Timing Requirements, I2C Timing
    23. 6.23 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Typical Device Jitter
      2. 8.3.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 8.3.3  VCO Calibration
      4. 8.3.4  Reference Divider (R)
      5. 8.3.5  Input Divider (M)
      6. 8.3.6  Feedback Divider (N)
      7. 8.3.7  Prescaler Dividers (PS_A, PS_B)
      8. 8.3.8  Phase Frequency Detector (PFD)
      9. 8.3.9  Charge Pump (CP)
      10. 8.3.10 Fractional Output Divider Jitter Performance
      11. 8.3.11 Device Block-Level Description
      12. 8.3.12 Device Configuration Control
      13. 8.3.13 Configuring the RESETN Pin
      14. 8.3.14 Preventing False Output Frequencies in SPI/I2C Mode at Start-Up
      15. 8.3.15 Input MUX and Smart Input MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1 Control Pins Definition
      2. 8.4.2 Loop Filter Recommendations for Pin Modes
      3. 8.4.3 Status Pins Definition
      4. 8.4.4 PLL Lock Detect
      5. 8.4.5 Interface and Control
        1. 8.4.5.1 Register File Reference Convention
        2. 8.4.5.2 SPI - Serial Peripheral Interface
          1. 8.4.5.2.1 Writing to the CDCM6208
          2. 8.4.5.2.2 Reading From the CDCM6208
          3. 8.4.5.2.3 Block Write/Read Operation
          4. 8.4.5.2.4 I2C Serial Interface
    5. 8.5 Programming
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1  Jitter Considerations in SERDES Systems
        2. 9.2.2.2  Jitter Considerations in ADC and DAC Systems
        3. 9.2.2.3  Configuring the PLL
        4. 9.2.2.4  Programmable Loop Filter
        5. 9.2.2.5  Loop filter Component Selection
        6. 9.2.2.6  Device Output Signaling
        7. 9.2.2.7  Integer Output Divider (IO)
        8. 9.2.2.8  Fractional Output Divider (FOD)
        9. 9.2.2.9  Output Synchronization
        10. 9.2.2.10 Output Mux on Y4 and Y5
        11. 9.2.2.11 Staggered CLK Output Power Up for Power Sequencing of a DSP
  10. 10Power Supply Recommendations
    1. 10.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 10.1.1 Mixing Supplies
      2. 10.1.2 Power-On Reset
      3. 10.1.3 Slow Power-Up Supply Ramp
      4. 10.1.4 Fast Power-Up Supply Ramp
      5. 10.1.5 Delaying VDD_Yx_Yy to Protect DSP IOs
    2. 10.2 Device Power-Up Timing
    3. 10.3 Power Down
    4. 10.4 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Reference Schematics
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.20 Device Individual Block Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.8 V, 2.5 V, or 3.3 V, TA = –40°C to 85°C, Output Types = LVPECL/CML/LVDS/LVCMOS/HCSL
BLOCKCONDITION TYPICAL CURRENT CONSUMPTION (mA)
Core CDCM6208 Core, active mode, PS_A = PS_B = 4 75
Output Buffer CML output, AC-coupled with 100-Ω diff load 24.25
LVPECL, AC-coupled with 100-Ω diff load 40
LVCMOS output, transient, 'C L' load, 'f' MHz output frequency, 'V' output swing 1.8 + V x f OUT x (C L+ 12 x 10 -12) x 10 3
LVDS output, AC-coupled with 100-Ω diff load 19.7
HCSL output, 50-Ω load to GND on each output pin 31
Output Divide Circuitry Integer Divider Bypass (Divide = 1) 3
Integer Divide Enabled, Divide > 1 8
Fractional Divider Enabled 12
additional current when PS_A differs from PS_B 15
Total Device, CDCM6208 Device Settings (V2)
  1. PRI input enabled, set to LVDS mode
  2. SEC input XTAL
  3. Input bypass off, PRI only sent to PLL
  4. Reference clock 30.72 MHz
  5. PRI input divider set to 1
  6. Reference input divider set to 1
  7. Charge Pump Current = 2.5 mA
  8. VCO Frequency = 3.072 GHz
  9. PS_A = PS_B divider ration = 4
  10. Feedback divider ratio = 25
  11. Output divider ratio = 5
  12. Fractional divider pre-divider = 2
  13. Fractional divider core input frequency = 384 MHz
  14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
  15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100 MHz, 66.66 MHz, 125 MHz, 50 MHz)		 (excl. I termination_resistors)
(1.8 V: 251 mA
2.5 V: 254 mA
3.3 V: 257 mA)
(incl. I termination_resistors)
(1.8 V: 310 mA
2.5 V: 313 mA
3.3 V: 316 mA)
Total Device, CDCM6208 Power Down (PDN = '0') 0.35

Helpful Note: The CDCM6208 User GUI does an excellent job estimating the total device current consumption based on the actual device configuration. Therefore, TI recommends using the GUI to estimate device power consumption.

The individual supply pin current consumption for Pin mode P23 was measured to come out the following:

Table 1. Individual Supplies Measured

Y0-1Y2-3Y4Y5Y6Y7SEC
(VSEC = 1.8V)		SEC
(VSEC = 2.5V)		PRIPLL1PLL2VCODVDDTotal
Customer EVM PWR PIN 39 = GND
VPRI = 1.8 V
VOUT = 1.8 V		 61 mA 40 mA 21 mA 29 mA 30 mA 31 mA 12 mA 70 mA 1.5 mA 295.5 mA