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  • CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

    • SNAS682 March   2016 CDCM6208V2G

      PRODUCTION DATA.  

  • CONTENTS
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  • CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematics
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information, Airflow = 0 LFM
    5. 8.5  Thermal Information, Airflow = 150 LFM
    6. 8.6  Thermal Information, Airflow = 250 LFM
    7. 8.7  Thermal Information, Airflow = 500 LFM
    8. 8.8  Single Ended Input Characteristics
    9. 8.9  Single Ended Input Characteristics (PRI_REF, SEC_REF)
    10. 8.10 Differential Input Characteristics (PRI_REF, SEC_REF)
    11. 8.11 Crystal Input Characteristics (SEC_REF)
    12. 8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)
    13. 8.13 PLL Characteristics
    14. 8.14 LVCMOS Output Characteristics
    15. 8.15 LVPECL (High-Swing CML) Output Characteristics
    16. 8.16 CML Output Characteristics
    17. 8.17 LVDS (Low-Power CML) Output Characteristics
    18. 8.18 HCSL Output Characteristics
    19. 8.19 Output Skew and Sync to Output Propagation Delay Characteristics
    20. 8.20 Device Individual Block Current Consumption
    21. 8.21 Worst Case Current Consumption
    22. 8.22 I2C TIMING
    23. 8.23 SPI Timing Requirements
    24. 8.24 Typical Characteristics
      1. 8.24.1 Fractional Output Divider Jitter Performance
      2. 8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency
  9. 9 Parameter Measurement Information
    1. 9.1 Characterization Test Setup
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
    4. 10.4 Device Functional Modes
      1. 10.4.1 Control Pins Definition
      2. 10.4.2 Loop Filter Recommendations for Pin Modes
      3. 10.4.3 Status Pins Definition
      4. 10.4.4 PLL Lock Detect
      5. 10.4.5 Interface and Control
        1. 10.4.5.1 Register File Reference Convention
        2. 10.4.5.2 SPI - Serial Peripheral Interface
          1. 10.4.5.2.1 Configuring the PLL
    5. 10.5 Programming
      1. 10.5.1 Writing to the CDCM6208V2G
      2. 10.5.2 Reading from the CDCM6208V2G
      3. 10.5.3 Block Write/Read Operation
      4. 10.5.4 I2C Serial Interface
    6. 10.6 Register Maps
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1  Device Block-level Description
        2. 11.2.1.2  Device Configuration Control
        3. 11.2.1.3  Configuring the RESETN Pin
        4. 11.2.1.4  Preventing False Output Frequencies in SPI/I2C Mode at Startup:
        5. 11.2.1.5  Power Down
        6. 11.2.1.6  Device Power Up Timing:
        7. 11.2.1.7  Input Mux and Smart Input Mux
        8. 11.2.1.8  Universal INPUT Buffer (PRI_REF, SEC_REF)
        9. 11.2.1.9  VCO Calibration
        10. 11.2.1.10 Reference Divider (R)
        11. 11.2.1.11 Input Divider (M)
        12. 11.2.1.12 Feedback Divider (N)
        13. 11.2.1.13 Prescaler Dividers (PS_A, PS_B)
        14. 11.2.1.14 Phase Frequency Detector (PFD)
        15. 11.2.1.15 Charge Pump (CP)
        16. 11.2.1.16 Programmable Loop Filter
          1. 11.2.1.16.1 Loop Filter Component Selection
          2. 11.2.1.16.2 Device Output Signaling
          3. 11.2.1.16.3 Integer Output Divider (IO)
          4. 11.2.1.16.4 Fractional Output Divider (FOD)
          5. 11.2.1.16.5 Output Synchronization
          6. 11.2.1.16.6 Output MUX on Y4 and Y5
          7. 11.2.1.16.7 Staggered CLK Output Powerup for Power Sequencing of a DSP
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Jitter Considerations in SERDES Systems
        2. 11.2.2.2 Jitter Considerations in ADC and DAC Systems
      3. 11.2.3 Application Performance Plots
        1. 11.2.3.1 Typical Device Jitter
  12. 12Power Supply Recommendations
    1. 12.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 12.1.1 Fast Power-up Supply Ramp
      2. 12.1.2 Delaying VDD_Yx_Yy to Protect DSP IOs
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
      1. 13.2.1 Reference Schematic
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information
  16. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RGZ|48
    • MPQF123F
Thermal pad, mechanical data (Package|Pins)
  • RGZ|48
    • QFND014T
Orderable Information
  • snas682_oa
  • snas682_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

CDCM6208V2G 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

1 Features

  • Superior Performance with Low Power:
    • Low Noise Synthesizer (265 fs-rms Typical Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms Typical Jitter)
    • 0.5 W Typical Power Consumption
    • High Channel-to-Channel Isolation and Excellent PSRR
    • Device Performance Customizable Through Flexible 1.8 V, 2.5 V and 3.3 V Power Supplies, Allowing Mixed Output Voltages
  • Flexible Frequency Planning:
    • 4x Integer Down-divided Differential Clock Outputs Supporting LVPECL-like, CML, or LVDS-like Signaling
    • 4x Fractional or Integer Divided Differential Clock Outputs Supporting HCSL, LVDS-like Signaling, or Eight CMOS Outputs
    • Fractional Output Divider Achieve 0 ppm to < 1 ppm Frequency Error and Eliminates need for Crystal Oscillators and Other Clock Generators
    • Output frequencies up to 800 MHz
  • Two Differential Inputs, XTAL Support, Ability for Smart Switching
  • SPI, I2C™, and Pin Programmable
  • Professional user GUI for Quick Design Turnaround
  • 7 x 7 mm 48-QFN package (RGZ)
  • -40 °C to 85 °C temperature range

2 Applications

  • Base Band Clocking (Wireless Infrastructure)
  • Networking and Data Communications
  • Keystone C66x Multicore DSP Clocking
  • Storage Server, Portable Test Equipment,
  • Medical Imaging, High End A/V

3 Description

The CDCM6208V2G is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V2G also features an innovative fractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V2G can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCM6208V2G VQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematics

CDCM6208V2G Gen_Des_SCAS931.gif
CDCM6208V2G synthesizer_mode_SCAS931.gif

5 Revision History

DATE REVISION NOTES
March 2016 * Initial release.

6 Description (continued)

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k - 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k - 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k - 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V2G is packaged in a small 48-pin 7 mm x 7 mm QFN package.

7 Pin Configuration and Functions

RGZ Package
48 Pin VQFN
Top View
CDCM6208V2G CDCM6208_Pin_Assignments_SCAS931.gif

Pin Functions

PIN I/O TYPE DESCRIPTION
NAME NO.
PRI_REFP 8 Input Universal Primary Reference Input +
PRI_REFN 9 Input Universal Primary Reference Input –
VDD_PRI_REF 7 PWR Analog Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to VDD_SEC_REF.
SEC_REFP 11 Input Universal Secondary Reference Input +
SEC_REFN 12 Input Universal Secondary Reference Input –
VDD_SEC_REF 10 PWR Analog Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to VDD_PRI_REF(2).
REF_SEL 6 Input LVCMOS
50kΩ pull-up		 Manual Reference Selection MUX for PLL. In SPI or I2C mode the reference selection is also controlled through Register 4 bit 12.
REF_SEL = 0 (≤ VIL): selects PRI_REF
REF_SEL = 1 (≥ VIH): selects SEC_REF (when Reg 4.12 = 1). See Table 35 for detail.
ELF 41 Output Analog External loop filter pin for PLL
Y0_P 14 Output Universal Output 0 Positive Terminal
Y0_N 15 Output Universal Output 0 Negative Terminal
Y1_P 17 Output Universal Output 1 Positive Terminal
Y1_N 16 Output Universal Output 1 Negative Terminal
VDD_Y0_Y1 (2 pins) 13, 18 PWR Analog Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V or 3.3 V
Y2_P 20 Output Universal Output 2 Positive Terminal
Y2_N 21 Output Universal Output 2 Negative Terminal
Y3_P 23 Output Universal Output 3 Positive Terminal
Y3_N 22 Output Universal Output 3 Negative Terminal
VDD_Y2_Y3 (2 pins) 19, 24 PWR Analog Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V or 3.3 V
Y4_P 26 Output Universal Output 4 Positive Terminal
Y4_N 25 Output Universal Output 4 Negative Terminal
VDD_Y4 27 PWR Analog Supply pin for output 4 to set between 1.8 V, 2.5 V or 3.3 V
Y5_P 29 Output Universal Output 5 Positive Terminal
Y5_N 28 Output Universal Output 5 Negative Terminal
VDD_Y5 30 PWR Analog Supply pin for output 5 to set between 1.8 V, 2.5 V or 3.3 V
Y6_P 32 Output Universal Output 6 Positive Terminal
Y6_N 33 Output Universal Output 6 Negative Terminal
VDD_Y6 31 PWR Analog Supply pin for output 6 to set between 1.8 V, 2.5 V or 3.3 V
Y7_P 35 Output Universal Output 7 Positive Terminal
Y7_N 36 Output Universal Output 7 Negative Terminal
VDD_Y7 34 PWR Analog Supply pin for output 7 to set between 1.8 V, 2.5 V or 3.3 V
VDD_VCO 39 PWR Analog Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The supply of this pin and the VDD_PLL2 supply pin can be combined as they are both analog and sensitive supplies
VDD_PLL1 37 PWR Analog Analog Power Supply Connections
VDD_PLL2 38 PWR Analog Analog Power Supply Connections; This pin is sensitive to power supply noise; The supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both power-sensitive, analog supply pins
DVDD 48 PWR Analog Digital Power Supply Connections; This is also the reference supply voltage for all control inputs and must match the expected input signal swing of control inputs.
GND PAD PWR Analog Power Supply Ground and Thermal Pad
STATUS0 46 Output LVCMOS Status pin 0 (see Table 6 for details)
STATUS1/PIN0 45 Output/
Input		 LVCMOS
no pull resistor		 STATUS1: Status pin in SPI/I2C modes. For details see Table 4 for pin modes and Table 6 for status mode.
PIN0: Control pin 0 in pin mode.
SI_MODE1 47 Input LVCMOS
50kΩ pull-up		 Serial Interface Mode or Pin mode selection.
SI_MODE[1:0]=00: SPI mode;
SI_MODE[1:0]=01: I2C mode;
SI_MODE[1:0]=10: Pin Mode (No serial programming);
SI_MODE[1:0]=11: RESERVED
SI_MODE0 1 Input LVCMOS
50kΩ pull-down
SDI/SDA/PIN1 2 Input/
Output		 LVCMOS in
Open drain out
LVCMOS in
no pull resistor		 SDI: SPI Serial Data Input
SDA: I2C Serial Data (Read/Write bi-directional), open drain output; requires a pull-up resistor in I2C mode;
PIN1: Control pin 1 in pin mode
SDO/AD0/PIN2 3 Output/
Input		 LVCMOS out
LVCMOS in
LVCMOS in
no pull resistor		 SDO: SPI Serial Data
AD0: I2C Address Offset Bit 0 input
PIN2: Control pin 2 in pin mode
SCS/AD1/PIN 3 4 Input LVCMOS
no pull resistor		 SCS: SPI Latch Enable
AD1: I2C Address Offset Bit 1 input
PIN3: Control pin 3 in pin mode
SCL/PIN4 5 Input LVCMOS
no pull resistor		 SCL: SPI/I2C Clock
PIN4: Control pin 4 in pin mode
RESETN/PWR 44 Input LVCMOS
50kΩ pull-up		 In SPI/I2C programming mode, external RESETN signal (active low).
RESETN = V IL: device in reset (registers values are retained)
RESETN = V IH: device active. The device can be programmed via SPI while RESETN is held low (this is useful to avoid any false output frequencies at power up). (1)
In Pin mode this pin controls device core and I/O supply voltage setting. 0 = 1.8 V, 1 = 2.5/3.3 V for the device core and I/O power supply voltage. In pin mode, it is not possible to mix and match the supplies. All supplies should either be 1.8 V or 2.5/3.3 V.
REG_CAP 40 Output Analog Regulator Capacitor; connect a 10 µF cap with ESR below 1 Ω to GND at frequencies above 100 kHz
PDN 43 Input LVCMOS
50kΩ pull-up		 Power Down Active low. When PDN = VIH is normal operation. When PDN = VIL, the device is disabled and current consumption minimized. Exiting power down resets the entire device and defaults all registers. It is recommended to connect a capacitor to GND to hold the device in power-down until the digital and PLL related power supplies are stable. See section on power down in the application section.
SYNCN 42 Input LVCMOS
50kΩ pull-up		 Active low. Device outputs are synchronized on a low-to-high transition on the SYNCN pin. SYNCN held low disables all outputs.
(1) Note: the device cannot be programmed in I2C while RESETN is held low.
(2) If Secondary input buffer is disabled (Register 4 Bit 5 = 0), it is possible to connect VDD_SEC_REF to GND.

8 Specifications

8.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN MAX UNIT
Supply Voltage Range, VDD_PRI, VDD_SEC, VDD_Yx_Yy, VDD_PLL[2:1], DVDD -0.5 4.6 V
Input Voltage Range CMOS control inputs, VIN -0.5 4.6
and
V DVDD+ 0.5		 V
Input Voltage Range PRI/SEC inputs 4.6
and
VVDDPRI.SEC+ 0.5		 V
Output Voltage Range, VOUT -0.5 VYxYy+ 0.5 V
Input Current, IIN 20 mA
Output Current, IOUT 50 mA
Junction Temperature, TJ 125 °C
Storage temperature range, Tstg -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute—maximum—rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD_Yx_Yy Output Supply Voltage 1.71 1.8/2.5/3.3 3.465 V
VDD_PLL1
VDD_PLL2		 Core Analog Supply Voltage 1.71 1.8/2.5/3.3 3.465 V
DVDD Core Digital Supply Voltage 1.71 1.8/2.5/3.3 3.465 V
VDD_PRI,
VDD_SEC		 Reference Input Supply Voltage 1.71 1.8/2.5/3.3 3.465 V
ΔVDD/Δt VDD power-up ramp time (0 to 3.3 V) PDN left open, all VDD tight together PDN low-high is delayed (1) 50 < tPDN ms
TA Ambient Temperature -40 85 °C
SDA and SCL in I 2 C MODE (SI_MODE[1:0] = 01)
VI Input Voltage DVDD = 1.8 V –0.5 2.45 V
DVDD = 3.3 V –0.5 3.965 V
dR Data Rate 100
400		 kbps
VIH High-level input voltage 0.7 x DVDD V
VIL Low-level input voltage 0.3 x DVDD V
CBUS_I2C Total capacitive load for each bus line 400 pF
(1) For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating. For slower power up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD, VDD_PLLx, and VDD_PRI/SEC reach at least 1.45V supply voltage. See application section on mixing power supplies and particularly Figure 57 for details.

8.4 Thermal Information, Airflow = 0 LFM(1) (2) (3) (4)

THERMAL METRIC(1) CDCM6208 UNIT
RGZ
48 PINS VQFN
RθJA Junction-to-ambient thermal resistance 30.27 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 16.58
RθJB Junction-to-board thermal resistance 6.83
ψJT Junction-to-top characterization parameter 0.23
ψJB Junction-to-board characterization parameter 6.8
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.06
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3) Connected to GND with 36 thermal vias (0.3 mm diameter).
(4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.5 Thermal Information, Airflow = 150 LFM(1) (2) (3) (4)

THERMAL METRIC(1) CDCM6208 UNIT
RGZ
48 PINS
RθJA Junction-to-ambient thermal resistance 21.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB Junction-to-board thermal resistance 6.61
ψJT Junction-to-top characterization parameter 0.37
ψJB Junction-to-board characterization parameter
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.06
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3) Connected to GND with 36 thermal vias (0.3 mm diameter).
(4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.6 Thermal Information, Airflow = 250 LFM(1) (2) (3) (4)

THERMAL METRIC(1) CDCM6208 UNIT
RGZ
48 PINS
RθJA Junction-to-ambient thermal resistance 19.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB Junction-to-board thermal resistance 6.6
ψJT Junction-to-top characterization parameter 0.45
ψJB Junction-to-board characterization parameter
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.06
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3) Connected to GND with 36 thermal vias (0.3 mm diameter).
(4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.7 Thermal Information, Airflow = 500 LFM(1) (2) (3) (4)

THERMAL METRIC(1) CDCM6208 UNIT
RGZ
48 PINS
RθJA Junction-to-ambient thermal resistance 17.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB Junction-to-board thermal resistance 6.58
ψJT Junction-to-top characterization parameter 0.58
ψJB Junction-to-board characterization parameter
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.05
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
(3) Connected to GND with 36 thermal vias (0.3 mm diameter).
(4) θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.

8.8 Single Ended Input Characteristics

(SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, SYNCN, REF_SEL), DVDD = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA = –40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH Input High Voltage 0.8 x DVDD V
VIL Input Low Voltage 0.2 x DVDD V
IIH Input High Current DVDD = 3.465V, VIH = 3.465 V (pull-up resistor excluded) 30 µA
IIL Input Low Current DVDD = 3.465V, VIL= 0 V -30 µA
ΔV/ΔT PDN, RESETN, SYNCN, REF_SEL Input Edge Rate 20% - 80% 0.75 V/ns
minPulse PDN, RESETN, SYNCN low pulse to trigger proper device reset 10 ns
C IN Input Capacitance 2.25 pF
RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]:
R Input Pullup and Pulldown Resistor 35 50 65 kΩ
SDA and SCL in I 2 C Mode (SI_MODE[1:0]=01)
VHYS_I2C Input hysteresis DVDD = 1.8 V 0.1 VDVDD V
DVDD = 2.5/3.3 V 0.05 VDVDD V
IH High-level input current VI = DVDD –5 5 µA
VOL Output Low Voltage IOL= 3mA 0.2 x DVDD V
CIN Input Capacitance terminal 5 pF

8.9 Single Ended Input Characteristics (PRI_REF, SEC_REF)

VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN Reference and Bypass Input Frequency VDD_PRI/SEC = 1.8 V 0.008 200 MHz
VDD_PRI/SEC = 3.3 V 0.008 250 MHz
VIH Input High Voltage 0.8 x VDD_PRI/VDD_SEC V
VIL Input Low Voltage 0.2 x VDD_PRI/VDD_SEC V
VHYST Input hysteresis 20 65 150 mV
IIH Input High Current VDD_PRI/VDD_SEC = 3.465 V, VIH = 3.465 V 30 µA
IIL Input Low Current VDD_PRI/VDD_SEC = 3.465 V, VIL = 0 V -30 µA
ΔV/ΔT Reference Input Edge Rate 20% - 80% 0.75 V/ns
IDC SE Reference Input Duty Cycle f PRI ≤ 200MHz 40% 60%
200 ≤ fPRI ≤ 250 MHz 43% 60%
CIN Input Capacitance 2.25 pF

8.10 Differential Input Characteristics (PRI_REF, SEC_REF)

VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fIN Reference and Bypass Input Frequency 0.008 250 MHz
VI Differential Input Voltage Swing, Peak-to-Peak VDD_PRI/SEC = 2.5/3.3 V 0.2 1.6 VPP
VDD_PRI/SEC = 1.8 V 0.2 1 VPP
VICM Input Common Mode Voltage CML input signaling, R4[7:6] = 00 VDD_PRI/VDD_SEC-0.4 VDD_PRI/VDD_SEC-0.1 V
VICM Input Common Mode Voltage LVDS, VDD_PRI/SEC
= 1.8/2.5/3.3 V,
R4[7:6] = 01, R4.1 = d.c.,
R4.0 = d.c.		 0.8 1.2 1.5 V
VHYST Input hysteresis LVDS (Q4[7:6,4:3] = 01) 15 65 mVpp
CML (Q4[7:6,4:3] = 00) 20 85 mVpp
IIH Input High Current VDD_PRI/SEC = 3.465 V, VIH = 3.465 V 30 µA
IIL Input Low Current VDD_PRI/SEC = 3.465V, VIL = 0 V -30 µA
ΔV/ΔT Reference Input Edge Rate 20% - 80% 0.75 V/ns
IDCDIFF Reference Input Duty Cycle 30% 70%
CIN Input Capacitance 2.7 pF

8.11 Crystal Input Characteristics (SEC_REF)

VDD_SEC = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V,TA = –40°C to 85°C
PARAMETER MIN TYP MAX UNIT
MODE OF OSCILLATION FUNDAMENTAL
Frequency See note (1) 10 30.72 MHz
See note (2) 30.73 50 MHz
Equivalent Series Resistance (ESR) 10 MHz 150(4) Ω
25 MHz 70(5)
50 MHz 30(6)
On-chip load capacitance 1.8 V / 3.3 V SEC_REFP 3.5 4.5 5.5 pF
1.8 V SEC_REFN 5.5 7.25 8.5
3.3 V SEC_REFN 6.5 7.34 8.5
Drive Level See note (3) 200 µW
(1) Verified with crystals specified for a load capacitance of CL=8pF, the pcb related capacitive load was estimated to be 2.3pF, and completed with a load capacitors of 4pF on each crystal terminal connected to GND. XTALs tested: NX3225GA 10MHz EXS00A-CG02813 CRG, NX3225GA 19.44MHz EXS00A-CG02810 CRG, NX3225GA 25MHz EXS00A-CG02811 CRG, and NX3225GA 30.72MHz EXS00A-CG02812 CRG.
(2) For 30.73 MHz to 50 MHz, it is recommended to verify sufficient negative resistance and initial frequency accuracy with the crystal vendor. The 50 MHz use case was verified with a NX3225GA 50MHz EXS00A-CG02814 CRG. To meet a minimum frequency error, the best choice of the XTAL was one with CL = 7pF instead of CL = 8pF.
(3) Maximum drive level measured was 145 µW; XTAL should at least tolerate 200 µW
(4) With NX3225GA_10M the measured remaining negative resistance on the EVM is 6430 Ω (43 x margin)
(5) With NX3225GA_25M the measured remaining negative resistance on the EVM is 1740 Ω (25 x margin)
(6) With NX3225GA_50M the measured remaining negative resistance on the EVM is 350 Ω (11 x margin)

8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V; TA = –40°C to 85°C (Output load capacitance 10 pF unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH Output High Voltage Status 1, Status 0, and SDO only; SDA is open drain and relies on external pullup for high output; IOH = 1 mA 0.8 x DVDD V
VOL Output Low Voltage IOL = 1 mA 0.2 x DVDD V
Vslew Output slew rate 30% - 70% 0.5 V/ns
IOZH 3-stat Output High Current DVDD = 3.465 V, VIH = 3.465 V 5 µA
IOZL 3-stat Output Low Current DVDD = 3.465 V, VIL = 0 V -5 µA
tLOS Status Loss of Signal Detection Time LOS_REFfvco 1 2 1/f PFD
tLOCK Status PLL Lock Detection Time Detect lock 2304 1/f PFD
Detect unlock 512

8.13 PLL Characteristics

VDD_PLLx, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fVCO VCO Frequency Range 2.39 2.55 GHz
KVCO VCO Gain 2.39 GHz 178 MHz/V
2.50 GHz 204
2.55 GHz 213
fPFD PFD Input Frequency 0.008 100 MHz
ICP-L High Impedance Mode Charge Pump Leakage ±700 nA
fFOM Estimated PLL Figure of Merit (FOM) Measured in-band phase noise at the VCO output minus 20log(N-divider) at the flat region –224 dBc/Hz
tSTARTUP Startup time (see Figure 41 ) Power supply ramp time of 1ms from 0 V to 1.7 V, final frequency accuracy of 10 ppm, fPFD = 25 MHz, CPDN_to_GND = 22nF
w/ PRI input signal 12.8 ms
w/ NDK 25 MHz crystal 12.85 ms

8.14 LVCMOS Output Characteristics

VDD_Yx_Yy = 1.71 V to 1.89V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT-F Output Frequency Fract Out divVDD_Yx_Yy = 2.5/3.3 V 0.78 250 MHz
Integer out divVDD_Yx_Yy = 2.5/3.3 V 1.55 250
Int or frac out divVDD_Yx_Yy = 1.8 V 0.78/1.5 200
fACC-F Output Frequency Error (1) Fractional Output Divider –1 1 ppm
VOH Output High Voltage (normal mode) VDD_Yx = min to max, IOH = -1 mA 0.8 x VDD_Yx_Yy V
VOL Output Low Voltage(normal mode) VDD_Yx = min to max, IOL = 100 µA 0.2 x VDD_Yx_Yy V
VOH Output High Voltage (slow mode) VDD_Yx = min to max, IOH = -100 µA 0.7 x VDD_Yx_Yy V
VOL Output Low Voltage(slow mode) VDD_Yx = min to max, IOL = 100 µA 0.3 x VDD_Yx_Yy V
IOH Output High Current V OUT = VDD_Yx_Yy/2
Normal mode –50 -8 mA
Slow mode –45 -5 mA
IOL Output Low Current V OUT = VDD_Yx_Yy/2
Normal mode 10 55 mA
Slow mode 5 40 mA
tSLEW-RATE-N Output Rise/Fall Slew Rate (normal mode) 20% to 80%, VDD_Yx_Yy = 2.5/3.3 V,
CL = 5 pF		 5.37 V/ns
Output Rise/Fall Slew Rate (normal mode) 20% to 80%, VDD_Yx_Yy = 1.8 V,
CL = 5 pF		 2.62 V/ns
tSLEW-RATE-S Output Rise/Fall Slew Rate (slow mode) 20% to 80%, VDD_Yx_Yy = 2.5/3.3 V,
CL = 5 pF		 4.17 V/ns
Output Rise/Fall Slew Rate (slow mode) 20% to 80%, VDD_Yx_Yy = 1.8 V,
CL = 5 pF		 1.46 V/ns
PN-floor Phase Noise Floor fOUT = 122.88 MHz –159.5 –154 dBc/Hz
ODC Output Duty Cycle Not in bypass mode 45% 55%
ROUT Output Impedance V OUT = VDD_Yx/2
Normal mode
Slow mode		 30
45		 50
74		 90
130		 Ω
(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of a multiple 1 over 220, the actual output frequency error is 0.
Note: In LVCMOS Mode, positive and negative outputs are in phase.

8.15 LVPECL (High-Swing CML) Output Characteristics

VDD_Yx_Yy = 1.71 V to 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT-I Output frequency Integer Output Divider 1.55 800 MHz
VCM-DC Output DC coupled common mode voltage DC coupled with 50 Ω external termination to VDD_Yx_Yy VDD_Yx_
Yy – 0.4		 V
|VOD| Differential output voltage 100 Ω diff load AC coupling (See Figure 11), fOUT ≤ 250 MHz
VDD_Yx_Yy ≤ 1.89 V 0.45 0.75 1.12 V
VDD_Yx_Yy ≥ 2.375 V 0.6 0.8 1.12 V
100 Ω diff load AC coupling (See Figure 11), fOUT ≥ 250 MHz
VDD_Yx_Yy ≤ 1.89 V 0.73 V
VDD_Yx_Yy ≥ 2.375 V 0.55 0.75 1.12 V
VOUT Differential output peak-to-peak voltage 2 x |VOD| V
tR/tF Output rise/fall time ±200 mV around crossing point 109 217 ps
20% to 80% VOD 211 ps
tslew Output rise/fall slew rate 3.7 5.1 7.3 V/ns
PN-floor Phase noise floor VDD_Yx_Yy = 3.3 V (See Figure 53) –161.4 –155.8 dBc/Hz
ODC Output duty cycle Not in bypass mode 47.5% 52.5%
ROUT Output impedance measured from pin to VDD_Yx_Yy 50 Ω

8.16 CML Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA = –40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT-I Output frequency Integer Output Divider 1.55 800 MHz
VCM-AC Output AC coupled common mode voltage AC coupled with 50 Ω receiver termination VDD_Yx_Yy – 0.46 V
VCM-DC Output DC coupled common mode voltage DC coupled with 50 Ω on-chip termination
to VDD_Yx_Yy		 VDD_Yx_Yy – 0.2 V
|VOD| Differential output voltage 100 Ω diff load AC coupling, (See Figure 11) 0.3 0.45 0.58 V
VOUT Differential output peak-to-peak voltage 2 x |VOD| V
tR/tF Output rise/fall time 20% to 80% VDDYx = 1.8 V 100 151 300 ps
VDDYx = 2.5 V/3.3 V 100 143 200 ps
PN-floor Phase noise floor at > 5 Hz offset fOUT = 122.88 MHz VDD_Yx_Yy = 1.8 V –161.2 –155.8 dBc/Hz
VDD_Yx_Yy = 3.3 V –161.2 –153.8 dBc/Hz
ODC Output duty cycle Not in bypass mode 47.5% 52.5%
ROUT Output impedance measured from pin to VDD_Yx_Yy 50 Ω

8.17 LVDS (Low-Power CML) Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465V, TA = –40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT-I Output frequency Integer output divider 1.55 400 MHz
fOUT-F Fractional output divider 0.78 400 MHz
fACC-F Output frequency error (1) Fractional output divider -1 1 ppm
VCM-AC Output AC coupled common mode voltage AC coupled with 50 Ω receiver termination VDD_Yx_Yy – 0.76 V
VCM-DC Output DC coupled common mode voltage DC coupled with 50 Ω on-chip termination to VDD_Yx_Yy VDD_Yx_Yy – 0.13 V
|VOD| Differential output voltage 100 Ω diff load AC coupling, (See Figure 11) 0.247 0.34 0.454 V
VOUT Differential output peak-to-peak voltage 2 x |VOD| V
tR/tF Output rise/fall time ±100mV around crossing point 300 ps
PN-floor Phase noise floor fOUT= 122.88 MHz VDD_Yx = 1.8 V –159.3 –154.5 dBc/Hz
VDD_Yx = 2.5/3.3 V –159.1 –154.9 dBc/Hz
ODC Output duty cycle Not in bypass mode Y[3:0] 47.5% 52.5%
Y[7:4] 45% 55%
ROUT Output impedance Measured from pin to VDD_Yx_Yy 167 Ω
(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of a multiple of 1 over 220, the actual output frequency error is 0.

8.18 HCSL Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT-I Output frequency Integer Output Divider 1.55 400 MHz
fOUT-F Fractional Output Divider 0.78 400 MHz
fACC-F Output Frequency Error (1) Fractional Output Divider -1 1 ppm
VCM Output Common Mode Voltage VDD_Yx_Yy = 2.5/3.3 V 0.2 0.34 0.55 V
VDD_Yx_Yy = 1.8 V 0.2 0.33 0.55 V
|VOD| Differential Output Voltage VDD_Yx_Yy = 2.5/3.3 V 0.4 0.67 1.0 V
VDD_Yx_Yy = 1.8 V 0.4 0.65 1.0 V
VOUT Differential Output Peak-to-peak Voltage VDD_Yx_Yy = 2.5/3.3 V 1.0 2.1 V
VDD_Yx_Yy = 1.8 V 2 x|VOD| V
tR/tF Output Rise/Fall Time Measured from VDIFF= –100 mV to
VDIFF = +100mV, VDD_Yx_Yy = 2.5/3.3 V		 100 167 250 ps
Measured from VDIFF= –100 mV to
VDIFF= +100 mV, VDD_Yx_Yy = 1.8 V		 120 192 295
PN-floor Phase Noise Floor fOUT = 122.88 MHz VDD_Yx_Yy = 1.8 V –158.8 –153 dBc/Hz
VDD_Yx = 2.5/3.3 V –157.6 –153 dBc/Hz
ODC Output Duty Cycle Not in bypass mode 45% 55%
(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of A 1/220 multiple, the actual output frequency error is 0.

8.19 Output Skew and Sync to Output Propagation Delay Characteristics

VDD_Yx_Yy = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465 V, TA = –40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPD-PS Propagation delay SYNCN↑ to output toggling high f VCO = 2.5 GHz PS_A = 4 9 10.5 11 1/fPS_A
PS_A = 5 9 10.2 11 1/fPS_A
PS_A = 6 9 10.0 11 1/fPS_A
ΔtPD-PS Part-to-Part Propagation delay variation SYNCN↑ to output toggling high(1) Fixed supply voltage, temp, and device setting(1) 0 1 1/f PS_A
OUTPUT SKEW – ALL OUTPUTS USE IDENTICAL OUTPUT SIGNALING, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
tSK,LVDS Skew between Y[7:4] LVDS Y[7:4] = LVDS 40 ps
tSK,LVDS Skew between Y[3:0] LVDS Y[3:0] = LVDS 40 ps
tSK,LVDS Skew between Y[7:0] LVDS Y[7:0] = LVDS 80 ps
tSK,CML Skew between Y[3:0] CML Y[3:0] = CML 40 ps
tSK,PECL Skew between Y[3:0] PECL Y[3:0] = LVPECL 40 ps
tSK,HCSL Skew between Y[7:4] HCSL Y[7:4] = HCSL 40 ps
tSK,SE Skew between Y[7:4] CMOS Y[7:4] = CMOS 50 ps
OUTPUT SKEW - MIXED SIGNAL OUTPUT CONFIGURATION, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
tSK,CMOS-LVDS Skew between Y[7:4] LVDS and CMOS mixed Y[4] = CMOS, Y[7:5] = LVDS 2.5 ns
tSK,CMOS-PECL Skew between Y[7:0] CMOS and LVPECL mixed Y[7:4] = CMOS, Y[3:0] = LVPECL 2.5 ns
tSK,PECL-LVDS Skew between Y[3:0] LVPECL and LVDS mixed Y[0] = LVPECL, Y[3:1] = LVDS 120 ps
tSK,PECL-CML Skew between Y[3:0] LVPECL and CML mixed Y[0] = LVPECL, Y[3:1] = CML 40 ps
tSK,LVDS-PECL Skew between Y[7:0] LVDS and LVPECL mixed Y[7:4] = LVDS, Y[3:0] = LVPECL 180 ps
tSK,LVDS-HCSL Skew between Y[7:4] LVDS and HCSL mixed Y[4] = LVDS, Y[7:5] = HCSL 250 ps
OUTPUT SKEW - USING FRACTIONAL OUTPUT DIVISION; PS_A = PS_B = 6, OutDiv = 3.125
tSK,DIFF, frac Skew between Y[7:4] LVDS using all fractional divider with the same divider setting Y[7:4] = LVDS 200 ps
(1) SYNC is toggled 10,000 times for each device. Test is repeated over process voltage and temperature (PVT).

8.20 Device Individual Block Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.8 V, 2.5 V, or 3.3 V, TA = –40°C to 85°C, Output Types = LVPECL/CML/LVDS/LVCMOS/HCSL
BLOCK CONDITION TYPICAL CURRENT CONSUMPTION (mA)
Core CDCM6208V2G Core, active mode, PS_A = PS_B = 4 75
Output Buffer CML output, AC coupled w/ 100 Ω diff load 24.25
LVPECL, AC coupled w/ 100 Ω diff load 40
LVCMOS output, transient, 'C L' load, 'f' MHz output frequency, 'V' output swing 1.8 + V x f OUT x (C L+ 12 x 10 -12) x 10 3
LVDS output, AC coupled w/ 100 Ω diff load 19.7
HCSL output, 50 Ω load to GND on each output pin 31
Output Divide Circuitry Integer Divider Bypass (Divide = 1) 3
Integer Divide Enabled, Divide > 1 8
Fractional Divider Enabled 12
additional current when PS_A differs from PS_B 15
Total Device, CDCM6208V2G Device Settings (V2)
  1. PRI input enabled, set to LVDS mode
  2. SEC input XTAL
  3. Input bypass off, PRI only sent to PLL
  4. Reference clock 30.72 MHz
  5. PRI input divider set to 1
  6. Reference input divider set to 1
  7. Charge Pump Current = 2.5 mA
  8. VCO Frequency = 3.072 GHz
  9. PS_A = PS_B divider ration = 4
  10. Feedback divider ratio = 25
  11. Output divider ratio = 5
  12. Fractional divider pre-divider = 2
  13. Fractional divider core input frequency = 384 MHz
  14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
  15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100 MHz, 66.66 MHz, 125 MHz, 50 MHz)		 (excl. I termination_resistors)
(1.8 V: 251 mA
2.5 V: 254 mA
3.3 V: 257 mA)
(incl. I termination_resistors)
(1.8 V: 310 mA
2.5 V: 313 mA
3.3 V: 316 mA)
Total Device, CDCM6208V2G Power Down (PDN = '0') 0.35

Helpful Note: The CDCM6208V2G User GUI does an excellent job estimating the total device current consumption based on the actual device configuration. Therefore, it is recommended to use the GUI to estimate device power consumption.

8.21 Worst Case Current Consumption

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 3.45 V, TA = T-40°C to 85°C, Output Types = maximum swing, all blocks including duty cycle correction and fractional divider enabled and operating at maximum operation
BLOCK CONDITION CURRENT CONSUMPTION
TYP / MAX
Total Device, CDCM6208V2G All conditions over PVT, AC coupled outputs with all outputs terminated, device configuration:
Device Settings (V2)
  1. PRI input enabled, set to LVDS mode
  2. SEC input XTAL
  3. Input bypass off, PRI only sent to PLL
  4. Reference clock 30.72 MHz
  5. PRI input divider set to 1
  6. Reference input divider set to 1
  7. Charge Pump Current = 2.5 mA
  8. VCO Frequency = 3.072 GHz
  9. PS_A = PS_B divider ration = 4
  10. Feedback divider ratio = 25
  11. Output divider ratio = 5
  12. Fractional divider pre-divider = 2
  13. Fractional divider core input frequency = 384 MHz
  14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
  15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100MHz, 66.66 MHz, 125 MHz, 50 MHz)		 1.8 V: 310 mA / +21% (excl term)
3.3 V: 318 mA / +21% (excl term)

8.22 I2C TIMING(2)

PARAMETER STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
fSCL SCL Clock Frequency 0 100 0 400 kHz
tsu(START) START Setup Time (SCL high before SDA low) 4.7 0.6 μs
th(START) START Hold Time (SCL low after SDA low) 4.0 0.6 μs
tw(SCLL) SCL Low-pulse duration 4.7 1.3 μs
tw(SCLH) SCL High-pulse duration 4.0 0.6 μs
th(SDA) SDA Hold Time (SDA valid after SCL low) 0 (1) 3.45 0 0.9 μs
tsu(SDA) SDA Setup Time 250 100 ns
tr-in SCL / SDA input rise time 1000 300 ns
tf-in SCL / SDA input fall time 300 300 ns
tf-out SDA Output fall time from VIH min to VIL max with a bus capacitance from 10 pF to 400 pF 250 250 ns
tsu(STOP) STOP Setup Time 4.0 0.6 μs
tBUS Bus free time between a STOP and START condition 4.7 1.3 μs
tglitch_filter Pulse width of spikes suppressed by the input glitch filter 75 300 75 300 ns
(1) The I2C master must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL.
(2) For additional information, refer to the I2C-Bus specification, Version 2.1 (January 2000); the CDCM6208V2G meets the switching characteristics for standard mode and fast mode transfer.
CDCM6208V2G CDCM6208_SPI_Port_Timing_SCAS931.gif Figure 1. CDCM6208V2G SPI Port Timing

8.23 SPI Timing Requirements

PARAMETER MIN NOM MAX UNIT
fClock Clock Frequency for the SCL 20 MHz
t1 SPI_LE to SCL setup time 10 ns
t2 SDI to SCL setup time 10 ns
t3 SDO to SCL hold time 10 ns
t4 SCL high duration 25 ns
t5 SCL low duration 25 ns
t6 SCL to SCS Setup time 10 ns
t7 SCS Pulse Width 20 ns
t8 SDI to SCL Data Valid (First Valid Bit after SCS) 10 ns
CDCM6208V2G I2C_Timing_Diagram_SCAS931.gif Figure 2. I2C Timing Diagram

8.24 Typical Characteristics

CDCM6208V2G Fractional_divider_bit_jitter_300_SCAS931.png
fFRAC = 300 MHz
Figure 3. Fractional Divider Bit Selection Impact on Jitter
CDCM6208V2G Fractional_divider_bit_TJ_SCAS931.gif
Figure 5. Fractional Divider Bit Selection Impact on TJ (Typical)
CDCM6208V2G PSRR_in_dBc_and_DJ_ps_SCAS931.gif
f OUT = 122 MHz
Figure 7. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format
CDCM6208V2G Fractional_divider_input_frequency_jitter_SCAS931.png
Using Divide by x.73 Example
Figure 4. Fractional Divider Input Frequency Impact on Jitter
CDCM6208V2G Fractional_divider_bit_TJ_voltage_SCAS931.gif
Figure 6. Fractional Divider Bit Selection Impact on TJ
(Maximum Jitter Across Process, Voltage & Temperature)

8.24.1 Fractional Output Divider Jitter Performance

The fractional output divider jitter performance is a function of the fraction output divider input frequency as well as actual fractional divide setting itself. To minimize the fractional output jitter, it is recommended to use the least number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 3, the largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits in the middle range of the fractional divider are selected. Tested using a LeCroy 40 Gbps RealTime scope over a time window of 200 ms. The RJ impact on TJ is estimated for a BERT 10(–12) – 1. This measurement result is overly pessimistic, as it does not bandwidth limit the high-frequencies. In a real system, the SERDES TX will BW limit the jitter through its PLL roll-off above the TX PLL bandwidth of typically bit rate divided by 10.

8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency

See Figure 7 for reference.

Many system designs become increasingly more sensitive to power supply noise rejection. In order to simplify design and cost, the CDCM6208V2G has built in internal voltage regulation, improving the power supply noise rejection over designs with no regulators. As a result, the following output rejection is achieved:

The DJ due to PSRR can be estimated using Equation 1:

Equation 1. CDCM6208V2G eq_determin_cas931.gif

Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the according output jitter for a 122.88 MHz output signal with LVDS signaling could be estimated with DJ = 0.7ps.

 
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