SNAS682 March   2016 CDCM6208V2G

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematics
  5. 5 Revision History
  6. 6 Description (continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information, Airflow = 0 LFM
    5. 8.5  Thermal Information, Airflow = 150 LFM
    6. 8.6  Thermal Information, Airflow = 250 LFM
    7. 8.7  Thermal Information, Airflow = 500 LFM
    8. 8.8  Single Ended Input Characteristics
    9. 8.9  Single Ended Input Characteristics (PRI_REF, SEC_REF)
    10. 8.10 Differential Input Characteristics (PRI_REF, SEC_REF)
    11. 8.11 Crystal Input Characteristics (SEC_REF)
    12. 8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)
    13. 8.13 PLL Characteristics
    14. 8.14 LVCMOS Output Characteristics
    15. 8.15 LVPECL (High-Swing CML) Output Characteristics
    16. 8.16 CML Output Characteristics
    17. 8.17 LVDS (Low-Power CML) Output Characteristics
    18. 8.18 HCSL Output Characteristics
    19. 8.19 Output Skew and Sync to Output Propagation Delay Characteristics
    20. 8.20 Device Individual Block Current Consumption
    21. 8.21 Worst Case Current Consumption
    22. 8.22 I2C TIMING
    23. 8.23 SPI Timing Requirements
    24. 8.24 Typical Characteristics
      1. 8.24.1 Fractional Output Divider Jitter Performance
      2. 8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency
  9. 9 Parameter Measurement Information
    1. 9.1 Characterization Test Setup
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
    4. 10.4 Device Functional Modes
      1. 10.4.1 Control Pins Definition
      2. 10.4.2 Loop Filter Recommendations for Pin Modes
      3. 10.4.3 Status Pins Definition
      4. 10.4.4 PLL Lock Detect
      5. 10.4.5 Interface and Control
        1. 10.4.5.1 Register File Reference Convention
        2. 10.4.5.2 SPI - Serial Peripheral Interface
          1. 10.4.5.2.1 Configuring the PLL
    5. 10.5 Programming
      1. 10.5.1 Writing to the CDCM6208V2G
      2. 10.5.2 Reading from the CDCM6208V2G
      3. 10.5.3 Block Write/Read Operation
      4. 10.5.4 I2C Serial Interface
    6. 10.6 Register Maps
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
        1. 11.2.1.1  Device Block-level Description
        2. 11.2.1.2  Device Configuration Control
        3. 11.2.1.3  Configuring the RESETN Pin
        4. 11.2.1.4  Preventing False Output Frequencies in SPI/I2C Mode at Startup:
        5. 11.2.1.5  Power Down
        6. 11.2.1.6  Device Power Up Timing:
        7. 11.2.1.7  Input Mux and Smart Input Mux
        8. 11.2.1.8  Universal INPUT Buffer (PRI_REF, SEC_REF)
        9. 11.2.1.9  VCO Calibration
        10. 11.2.1.10 Reference Divider (R)
        11. 11.2.1.11 Input Divider (M)
        12. 11.2.1.12 Feedback Divider (N)
        13. 11.2.1.13 Prescaler Dividers (PS_A, PS_B)
        14. 11.2.1.14 Phase Frequency Detector (PFD)
        15. 11.2.1.15 Charge Pump (CP)
        16. 11.2.1.16 Programmable Loop Filter
          1. 11.2.1.16.1 Loop Filter Component Selection
          2. 11.2.1.16.2 Device Output Signaling
          3. 11.2.1.16.3 Integer Output Divider (IO)
          4. 11.2.1.16.4 Fractional Output Divider (FOD)
          5. 11.2.1.16.5 Output Synchronization
          6. 11.2.1.16.6 Output MUX on Y4 and Y5
          7. 11.2.1.16.7 Staggered CLK Output Powerup for Power Sequencing of a DSP
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Jitter Considerations in SERDES Systems
        2. 11.2.2.2 Jitter Considerations in ADC and DAC Systems
      3. 11.2.3 Application Performance Plots
        1. 11.2.3.1 Typical Device Jitter
  12. 12Power Supply Recommendations
    1. 12.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 12.1.1 Fast Power-up Supply Ramp
      2. 12.1.2 Delaying VDD_Yx_Yy to Protect DSP IOs
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
      1. 13.2.1 Reference Schematic
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

14 Device and Documentation Support

14.1 Documentation Support

14.1.1 Related Documentation

IC Package Thermal Metrics application report, SPRA953.

Hardware Design Guide for KeyStone Devices SPRABI2 for the SRIO interface.

14.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

14.3 Trademarks

KeyStone, E2E are trademarks of Texas Instruments.

I2C is a trademark of NXP B.V. Corporation.

All other trademarks are the property of their respective owners.

14.4 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

14.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.