SCAS793G June   2005  – August 2017 CDCM7005

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic/Manual Reference Clock Switching
      2. 9.3.2 PLL Lock for Analog and Digital Detect
        1. 9.3.2.1 PLL Lock/Out-of-Lock Definition
        2. 9.3.2.2 Digital vs Analog Lock
      3. 9.3.3 Differential LVPECL Outputs and Single-Ended LVCMOS Outputs
      4. 9.3.4 Frequency Hold-Over Mode
      5. 9.3.5 Charge Pump Preset to VCC_CP/2
      6. 9.3.6 Charge Pump Current Direction
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SPI Control Interface
      2. 9.5.2 Functional Description of the Logic
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Application Information on the Clock Generation for Interpolating DACs With the CDCM7005
        1. 10.1.1.1 AC-Coupled Interface to ADC/DAC
      2. 10.1.2 Phase Noise
      3. 10.1.3 In-Band Noise Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGZ|48
  • ZVA|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC, AVCC, VCC_CP Supply voltage (2) –0.5 4.6 V
VI Input voltage (3) –0.5 VCC + 0.5 V
VO Output voltage (3) –0.5 VCC + 0.5 V
IOUT Output current for LVPECL/LVCMOS outputs
(0 < VO < VCC)		 ±50 mA
IIN Input current (VI < 0, VI > VCC) ±20 mA
TJ Maximum junction temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All supply voltages have to be supplied at the same time.
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC, AVCC Supply voltage 3 3.3 3.6 V
VCC_CP 2.3 VCC
VIL Low-level input voltage LVCMOS, see (2) 0.3 VCC V
VIH High-level input voltage LVCMOS, see (2) 0.7 VCC V
IOH High-level output current LVCMOS (includes all status pins) –8 mA
IOL Low-level output current LVCMOS (includes all status pins) 8 mA
VI Input voltage range LVCMOS 0 3.6 V
VINPP Input amplitude LVPECL (VVCXO_IN – V VCXO_IN )(1) 0.5 1.3 V
VIC Common-mode input voltage LVPECL 1 VCC–0.3 V
TA Operating free-air temperature –40 85 °C
(1) VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP
of 150 mV.
(2) VIL and VIH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an ac-coupling to VCC/2 is provided.

7.4 Thermal Information

THERMAL METRIC(1) RGZ AIRFLOW (lfm) ZVA AIRFLOW (m/s) CDCM7005 UNIT
RGZ (VQFN) ZVA (BGA)
48 PINS 64 PINS
RθJA Junction-to-ambient thermal resistance 0 0 29.9 53.9 °C/W
150 1 24.7 49.8
250 2 23.2 48.5
500 – 21.5 –
RθJC(top) Junction-to-case (top) thermal resistance 22.4 28.3 °C/W
RθJB Junction-to-board thermal resistance 14.2 38.6 °C/W
ψJT Junction-to-top characterization parameter 0 0 0.2 0.7 °C/W
150 1 0.2 0.7
250 2 0.2 0.8
500 – 0.3 –
ψJB Junction-to-board characterization parameter – – °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
OVERALL
ICC_LVPECL Supply current (ICC over frequency see Figure 1 through Figure 4) fVCXO = 245.76 MHz,
fREF_IN = 30.72 MHz,
PFD = 240 kHz, ICP = 2 mA, all outputs are LVPECL and Div-by-8 (load, see Figure 13)		 210 260 mA
ICC_LVCMOS fVCXO = 245.76 MHz,
fREF_IN = 30.72 MHz,
PFD = 240 kHz, ICP = 2 mA, All outputs are LVCMOS and Div-by-8 (load, 10 pF)		 120 150 mA
ICCPD Power-down current fIN = 0 MHz, VCC = 3.6 V, AVCC = 3.6 V,
VCC_CP = 3.6 V,
VI = 0 V or VCC 		100 300 µA
IOZ High-impedance state output current for Yx outputs VO = 0 V or VCC – 0.8 V ±40 µA
VO = 0 V or VCC ±100 µA
VI_REF_CP Voltage on I_REF_CP (external current path for accurate charge pump current) 12 kΩ to GND at pin D8 (BGA), pin 22 (QFN) 1.21 V
VBB Output reference voltage VCC = 3 V – 3.6 V; IBB = –0.2 mA VCC–1.3 V
CO Output capacitance for Yx VCC = 3.3 V, VO = 0 V or VCC 2 pF
CI Input capacitance at PRI_REF and SEC_REF VI = 0 V or VCC, VI = 0 V or VCC 2.7 pF
Input capacitance at CTRL_LE, CTRL_CLOCK, CTRL_DATA VI = 0 V or VCC 2
LVCMOS
fclk Output frequency, see (2), (3), Figure 6, and Figure 7 Load = 5 pF to GND, 1 kΩ to VCC, 1 kΩ to GND 250 MHz
VIK LVCMOS input clamp voltage VCC = 3 V, II = –18 mA –1.2 V
II LVCMOS input current for CTRL_LE, CTRL_CLK, CTRL_DATA VI = 0 V or VCC, VCC = 3.6 V ±5 µA
IIH LVCMOS input current for PD, RESET, HOLD, REF_SEL, PRI_REF, SEC_REF, (see (4)) VI = VCC, VCC = 3.6 V 5 µA
IIL LVCMOS input current for PD, RESET, HOLD, REF_SEL, PRI_REF, SEC_REF, (see (4)) VI = 0 V, VCC = 3.6 V –15 –35 µA
VOH High-level output voltage for LVCMOS outputs VCC = min to max,
IOH = –100 μA 		VCC–0.1 V
VCC = 3 V, IOH = –6 mA 2.4
VCC = 3 V, IOH = –12 mA 2
VOL Low-level output voltage for LVCMOS outputs VCC = min to max,
IOL = 100 μA 		0.1 V
VCC = 3 V, IOL = 6 mA 0.5
VCC = 3 V, IOL = 12 mA 0.8
IOH High-level output current VCC = 3.3 V, VO = 1.65 V –30 mA
IOL Low-level output current VCC = 3.3 V, VO = 1.65 V 33 mA
tpho Phase offset (REF_IN to Y output)(6) VREF_IN = VCC/2, Y = VCC/2,
see Figure 11, Load = 10 pF		 1.8 ns
tsk(p) LVCMOS pulse skew, see Figure 10 Crosspoint to VCC/2 load, see Figure 12 150 ps
tpd(LH) Propagation delay from VCXO_IN to Yx, see Figure 10 Crosspoint to VCC/2,
Load = 10 pF, see Figure 12 (PLL bypass mode)		 2 2.5 3 ns
tpd(HL)
tsk(o) LVCMOS single-ended output skew, see (7) and Figure 10 All outputs have the same divider ratio 55 ps
Outputs have different divider ratios 70
Duty cycle LVCMOS VCC/2 to VCC/2 49% 51%
tslew-rate Output rise/fall slew rate 20% to 80% of swing (load
see Figure 12)		 2.4 3.5 V/ns
LVPECL
fclk Output frequency, see (3) and Figure 5 Load, see Figure 13 0 1500 MHz
II LVPECL input current VI = 0 V or VCC ±20 µA
VOH LVPECL high-level output voltage Load, See Figure 13 VCC–1.18 VCC–0.81 V
VOL LVPECL low-level output voltage Load, See Figure 13 VCC–2 VCC–1.55 V
|VOD| Differential output voltage See Figure 9 and load, see Figure 13 500 mV
tpho Phase offset (REF_IN to Y output)(7) VREF_IN = VCC/2 to cross point of Y, see Figure 11 –200 100 ps
tpd(LH) Propagation delay time, VCXO_IN to Yx, see Figure 10 Cross point-to-cross point, load
see Figure 13 		340 490 640 ps
tpd(HL)
tsk(p) LVPECL pulse skew, see Figure 10 Cross point-to-cross point, load
see Figure 13 		10 ps
tsk(o) LVPECL output skew(7) Load see Figure 13, all outputs have the same divider ratio 20 ps
Load see Figure 13, outputs have
different divider ratios		 50
tr / tf Rise and fall time 20% to 80% of VOUTPP, see Figure 9 120 170 220 ps
CI Input capacitance at VCXO_IN, VCXO_IN 1.5 pF
LVCMOS-TO-LVPECL
tsk(P_C) Output skew between LVCMOS and LVPECL outputs, see (8) and Figure 10 Cross point to VCC/2; load,
see Figure 12 and Figure 13 		1.7 2 2.4 ns
PLL ANALOG LOCK
IOH High-level output current VCC = 3.6 V, VO = 1.8 V –110 µA
IOL Low-level output current VCC = 3.6 V, VO = 1.8 V 110 µA
IOZH LOCK High-impedance state output current for PLL LOCK output(5) VO = 3.6 V (PD is set low) 45 65 µA
IOZL LOCK High-impedance state output current for PLL LOCK output(5) VO = 0 V (PD is set low) ±5 µA
VIT+ Positive input threshold voltage VCC = min to max VCC×0.55 V
VIT– Negative input threshold voltage VCC = min to max VCC×0.35 V
PHASE DETECTOR
fCPmax Maximum charge pump frequency Default PFD pulse width delay 100 MHz
CHARGE PUMP
ICP Charge pump sink/source current range (9) VCP = 0.5 VCC_CP ±0.2 ±3 mA
ICP3St Charge pump 3-state current 0.5 V < VCP < VCC_CP – 0.5 V 10 nA
ICPA ICP absolute accuracy VCP = 0.5 VCC_CP, internal reference resistor, SPI default settings 10%
VCP = 0.5 VCC_CP, external reference resistor 12 kΩ (1%) at I_REF_CP, SPI default settings 5%
ICPM Sink/source current matching 0.5 V < VCP < VCC_CP – 0.5 V, SPI default settings 2.5%
IVCPM ICP vs VCP matching 0.5 V < VCP < VCC_CP – 0.5 V 5%
(1) All typical values are at VCC = 3.3 V, temperature = 25°C.
(2) fclk can be up to 400 MHz in the typical operating mode (25°C / 3.3-V VCC). The total power consumption limit of 700 mW for the BGA package can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4).
(3) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification.
(4) These inputs have an internal 150-kΩ pullup resistor.
(5) Lock output has an 80-kΩ pulldown resistor.
(6) This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M and VCXO delay N).
(7) The tsk(o) specification is only valid for equal loading of all outputs.
(8) The phase of LVCMOS is lagging in reference to the phase of LVPECL.
(9) Defined by SPI settings.

7.6 Timing Requirements

over recommended ranges of supply voltage, load and operating free air temperature
MIN NOM MAX UNIT
PRI_REF/SEC_REF_IN REQUIREMENTS
fREF_IN LVCMOS primary or secondary reference clock frequency(1) (4) 0 200 MHz
tr/ tf Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of VCC 4 ns
dutyREF Duty cycle of PRI_REF or SEC_REF at VCC/2 40% 60%
VCXO_IN, VCXO_IN REQUIREMENTS
fVCXO_IN VCXO clock frequency(2) 0 2200 MHz
tr/ tf Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz(3) 3 ns
dutyVCXO Duty cycle of VCXO clock 40% 60%
SPI/CONTROL REQUIREMENTS (see Figure 23)
fCTRL_CLK CTRL_CLK frequency 20 MHz
tsu1 CTRL_DATA to CTRL_CLK setup time 10 ns
th2 CTRL_DATA to CTRL_CLK hold time 10 ns
t3 CTRL_CLK high duration 25 ns
t4 CTRL_CLK low duration 25 ns
tsu5 CTRL_LE to CTRL_CLK setup time 10 ns
tsu6 CTRL_CLK to CTRL_LE setup time 10 ns
t7 CTRL_LE pulse width 20 ns
tr/ tf Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC 4 ns
PD, RESET, HOLD, REF_SEL REQUIREMENTS
tr / tf Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of VCC 4 ns
(1) At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.
(2) If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!
(3) Use a square wave for lower frequencies (< 80 MHz).
(4) fREF_IN can be up to 250 MHz in typical operating mode (25°C / 3.3-V VCC).

7.7 Typical Characteristics

CDCM7005 scas793_g001.gif
If div-by-2/4/8/16 is activated for one or more outputs, 'Δ for div-by-2/4/8/16' has to be added to ICC of div-by-1. If div-by-3 or div-by-6 is activated, 'Δ for div-by-2/4/8/16' and 'Δ for div-by3/6' has to be added to ICC of div-by-1.
Figure 1. LVPECL Supply Current vs Number of Active Outputs
CDCM7005 scas793_g003_.gif
To estimate ICC with different P-divider settings use 'Δ for div-by-2/4/8/16' and 'Δ for div-by-3/6' of Figure 1.
It is not recommended to exceed power dissipation of 700 mW for the BGA package at TA 85°C.
Figure 3. LVCMOS Supply Current and Device Power Consumption vs Number of Active Outputs (Load = 5 pF)
CDCM7005 scas793_g005.gif Figure 5. Differential LVPECL Output Voltage vs Output Frequency
CDCM7005 scas793_g007.gif Figure 7. LVCMOS Output Swing vs Frequency
CDCM7005 scas793_g002.gif
Figure 2. LVPECL Device Power Consumption vs Number of Active Outputs
CDCM7005 scas793_g004_.gif
To estimate ICC with different P-divider settings use 'Δ for div-by-2/4/8/16' and 'Δ for div-by-3/6' of Figure 1.
It is not recommended to exceed power dissipation of 700 mW for the BGA package at TA 85°C.
Figure 4. LVCMOS Supply Current and Device Power Consumption vs Number of Active Outputs (Load = 10 pF)
CDCM7005 scas793_g006.gif Figure 6. LVCMOS Output Swing vs Frequency
CDCM7005 scas793_g008.gif Figure 8. Output Reference Voltage (VBB) vs Load