The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
CDCM9102 | VQFN (32) | 5.00 mm × 5.00 mm |
Changes from * Revision (February 2012) to A Revision
PACKAGED DEVICES | FEATURES | TA |
---|---|---|
CDCM9102RHBT | 32-pin VQFN (RHB) package, small tape and reel | –40°C to 85°C |
CDCM9102RHBR | 32-pin VQFN (RHB) package, tape and reel |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
POWER SUPPLIES | |||
GND | Thermal pad, 14, 22 | G | Power supply ground and thermal relief |
REGCAP1 | 19 | P | Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND |
REGCAP2 | 17 | P | Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND |
VDD1 | 4 | P | Power Supply, OUT0 clock port |
VDD2 | 1 | P | Power Supply, OUT1 clock port |
VDD3 | 9 | P | Power supply, low-noise clock generator |
VDD4 | 16 | P | Power supply, low-noise clock generator |
VDD5 | 18 | P | Power supply, low-noise clock generator |
VDD6 | 20 | P | Power supply, crystal oscillator input |
DEVICE CONFIGURATION AND CONTROL | |||
NC | 8, 13, 15, 24–32 | — | No connection permitted |
OE | 7 | O | Output enable/shutdown control input (see Table 2) |
OS1 | 10 | O | Output format select control inputs (see Table 3) |
OS0 | 11 | O | Output format select control inputs (see Table 3) |
RESET | 12 | I | Device reset input (active-low) (see Table 4)(2) |
CRYSTAL OSCILLATOR | |||
XIN | 21 | I | Parallel resonant crystal input (25 MHz) |
DEVICE OUTPUTS | |||
OSCOUT | 23 | O | Oscillator output port (25 MHz) |
OUT0N | 5 | O | Output 0 – negative terminal (100 MHz) |
OUT0P | 6 | O | Output 0 – positive terminal (100 MHz) |
OUT1N | 2 | O | Output 1 – negative terminal (100 MHz) |
OUT1P | 3 | O | Output 1 – positive terminal (100 MHz) |
MIN | MAX | UNIT | ||
---|---|---|---|---|
IIN | Input current | 20 | mA | |
IOUT | Output current | 50 | mA | |
VDDx | Supply voltage(2) | –0.5 | 4.6 | V |
VIN | Input voltage(3) | –0.5 | VDDx + 0.5 | V |
VOUT | Output voltage(3) | –0.5 | VDDx + 0.5 | V |
TA | Operating temperature | 85 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDDX | DC power-supply voltage | 3 | 3.3 | 3.6 | V |
TA | Ambient temperature | –40 | 85 | °C |
THERMAL METRIC(1)(2) | CDCM9102 | UNIT | |
---|---|---|---|
RHB (VQFN) | |||
32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 33.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 25.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 0.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 7.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.12 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
LVCMOS INPUTS(1) | ||||||
VIH | Input high voltage | 0.6 × VDD | V | |||
VIL | Input low voltage | 0.4 × VDD | V | |||
IIH | Input high current | VDD = 3.6 V, VIL = 0 V | 200 | µA | ||
IIL | Input low current | VDD = 3 V, VIH = 3.6 V | –200 | µA | ||
CIN | Input capacitance | 8 | 10 | pF | ||
RPU | Input pullup resistor | 150 | kΩ | |||
CRYSTAL CHARACTERISTICS (XIN)(2) | ||||||
fXTAL | Crystal input frequency | Fundamental mode | 25 | MHz | ||
ESR | Effective series resistance of crystal | 50 | Ω | |||
CIN | On-chip load capacitance | 8 | 10 | pF | ||
XTALDL | Maximum drive level - XTAL | 0.1 | 1 | mW | ||
CSHUNT | Maximum shunt capacitance | 7 | pF | |||
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVPECL)(3) | ||||||
VOH | Output high voltage | VDD – 1.18 | VDD – 0.73 | V | ||
VOL | Output low voltage | VDD – 2 | VDD – 1.55 | V | ||
|VOD| | Differential output voltage | 0.6 | 1.23 | V | ||
tR and tF | Output rise and fall time | 20% to 80% | 175 | ps | ||
ODC | Output duty cycle | 45% | 55% | |||
tSKEW | Skew between outputs | 20 | ps | |||
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVDS)(4) | ||||||
|VOD| | Differential output voltage | 0.247 | 0.454 | V | ||
ΔVOD | VOD magnitude change | 50 | mV | |||
VOS | Common-mode voltage | 1.125 | 1.375 | V | ||
ΔVOS | VOS magnitude change | 50 | mV | |||
tR and tF | Output rise and fall time | 20% to 80% | 255 | ps | ||
ODC | Output duty cycle | 45% | 55% | |||
tSKEW | Skew between outputs | 30 | ps | |||
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVCMOS)(5) | ||||||
VOH | Output high voltage | VCC = 3 V to 3.6 V, IOH = –100 µA | VDD – 0.5 | V | ||
VOL | Output low voltage | VCC = 3 V to 3.6 V, IOH = 100 µA | 0.3 | V | ||
tSLEW | Output rise/fall slew rate | 20% to 80% | 2.4 | V/ns | ||
ODC | Output duty cycle | 45% | 55% | |||
tSKEW | Skew between outputs | 50 | ps |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|
LVCMOS OUTPUT MODE | ||||
Random jitter | 507 | fs RMS | ||
Period jitter | 24.5 | ps pk-pk | ||
LVPECL OUTPUT MODE | ||||
Random jitter | 510 | fs RMS | ||
Period jitter | 20.7 | ps pk-pk | ||
LVDS OUTPUT MODE | ||||
Random jitter | 533 | fs RMS | ||
Period jitter | 26.5 | ps pk-pk |
The CDCM9102 is a high-performance PLL that generates 2 copies of commonly-used reference clocks with less than 1-ps RMS jitter from a low-cost crystal.
The CDCM9102 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a crystal input interface, a phase frequency detector (PFD), a charge pump, an on-chip loop filter, and prescaler and feedback dividers. Completing the CDCM9102 device are the output divider and universal output buffer. The PLL and output divider are pre-programmed to generate 2 copies of 100 MHz in LVCMOS, LVPECL or LVDS format.
The PLL is powered by on-chip, low-dropout (LDO) linear voltage regulators. The regulated supply network is partitioned such that the sensitive analog supplies are powered from separate LDOs rather than the digital supplies which use a separate LDO regulator. These LDOs provide isolation for the PLL from any noise in the external power-supply rail. The REG_CAP1 and REG_CAP2 pins should each be connected to ground by 10-μF capacitors to ensure stability.
The CDCM9102 implements a Colpitts oscillator; therefore, one side of the crystal connects to the XIN pin and the other crystal terminal connects to ground. The device requires the use of a fundamental-mode crystal, and the oscillator operates in parallel resonance mode. The correct load capacitance is necessary to ensure that the circuit oscillates properly. The load capacitance comprises all capacitances in the oscillator feedback loop (the capacitances seen between the terminals of the crystal in the circuit). It is important to account for all sources of capacitance when calculating the correct value for the external discrete load capacitance shown in Figure 8.
The CDCM9102 has been characterized with 10-pF parallel-resonant crystals. The input stage of the crystal oscillator in the CDCM9102 is designed to oscillate at the correct frequency for all parallel-resonant crystals with low-pull capability and rated with a load capacitance that is equal to the sum of the on-chip load capacitance at the XIN pin (CIN = 10 pF maximum), crystal stray capacitance, and board parasitic capacitance between the crystal and XIN pin. To minimize stray and parasitic capacitances, minimize the trace distance routed from the crystal to the XIN pin and avoid other active traces and active circuitry in the area of the crystal oscillator circuit. Table 1 lists crystal types that have been evaluated with the CDCM9102.
MANUFACTURER | PART NUMBER |
---|---|
Vectron | VXC1-1134 25M0000000 |
Fox | 218-3 |
Saronix | FP2500002 |
A mismatch of the load capacitance results in a frequency error according to Equation 1.
where
The difference between the rated load capacitance (from the crystal datasheet) and the actual load capacitance (CLa = CIN + CL + CSTRAY + CPARASITIC) should be minimized. A crystal with a low pullability rating (low CS) is ideal.
Design Example:
Desired frequency tolerance Δf ≤ ±80 ppm
Crystal Vendor Parameters:
Intrinsic Frequency Tolerance = ±30 ppm
C0 = 7 pF (shunt capacitance)
CS = 10 fF (motional capacitance)
CLr = 12 pF (load capacitance)
Substituting these parameters into Equation 1 yields a maximum value of CLa = 17 pF to achieve the desired Δf (±50 ppm). Recall that CLa = CIN + CL + CSTRAY + CPARASITIC = 8 pF + (CL + CSTRAY + CPARASITIC). Ideally, the load presented to this crystal should be 12 pF; therefore, the sum of (CL + CSTRAY + CPARASITIC) must be less than 9 pF. Stray and parasitic capacitance must be controlled. This is because the Colpitts oscillator is particularly sensitive to capacitance in parallel with the crystal; therefore, good layout practice is essential. TI recommends that the designer extract the stray and parasitic capacitance from the printed-circuit board design tool and adjust CL accordingly to achieve CLr = CLa. In common scenarios, the external load capacitor is often unnecessary; however, TI recommends that pads be implemented to accommodate an external load capacitor so that the ppm error can be minimized.
Certain PCI Express applications require HCSL signaling. Because the common-mode voltage for LVPECL and HCSL are different, applications requiring HCSL signaling must use AC-coupling as shown in Figure 9. The
150-Ω resistors ensure proper biasing of the CDCM9102 LVPECL output stage. The 471-Ω and 56-Ω resistor network biases the HCSL receiver input stage.
Table 2 and Table 3 list the pin controls and pin configurations of the CDCM9102 output. Table 4 lists the device reset.
OE (Pin 7) | MODE | DEVICE CORE | OUTPUT |
---|---|---|---|
0 | Power down | Power down | Hi-Z |
1 | Normal | Active | Active |
CONTROL PINS | OUTPUT MODE | |
---|---|---|
OS1 (Pin 10) | OS0 (Pin 11) | |
0 | 0 | LVCMOS, OSCOUT = OFF |
0 | 1 | LVDS, OSCOUT = OFF |
1 | 0 | LVPECL, OSCOUT = OFF |
1 | 1 | LVPECL, OSCOUT = ON |
RESET (Pin 12) | OPERATING MODE | DEVICE OUTPUTS |
---|---|---|
0 | Device reset | Hi-Z |
0 → 1 | Clock generator calibration | Hi-Z |
1 | Normal | Active |