The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
CDCM9102 | VQFN (32) | 5.00 mm × 5.00 mm |
Changes from * Revision (February 2012) to A Revision
PACKAGED DEVICES | FEATURES | TA |
---|---|---|
CDCM9102RHBT | 32-pin VQFN (RHB) package, small tape and reel | –40°C to 85°C |
CDCM9102RHBR | 32-pin VQFN (RHB) package, tape and reel |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
POWER SUPPLIES | |||
GND | Thermal pad, 14, 22 | G | Power supply ground and thermal relief |
REGCAP1 | 19 | P | Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND |
REGCAP2 | 17 | P | Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND |
VDD1 | 4 | P | Power Supply, OUT0 clock port |
VDD2 | 1 | P | Power Supply, OUT1 clock port |
VDD3 | 9 | P | Power supply, low-noise clock generator |
VDD4 | 16 | P | Power supply, low-noise clock generator |
VDD5 | 18 | P | Power supply, low-noise clock generator |
VDD6 | 20 | P | Power supply, crystal oscillator input |
DEVICE CONFIGURATION AND CONTROL | |||
NC | 8, 13, 15, 24–32 | — | No connection permitted |
OE | 7 | O | Output enable/shutdown control input (see Table 2) |
OS1 | 10 | O | Output format select control inputs (see Table 3) |
OS0 | 11 | O | Output format select control inputs (see Table 3) |
RESET | 12 | I | Device reset input (active-low) (see Table 4)(2) |
CRYSTAL OSCILLATOR | |||
XIN | 21 | I | Parallel resonant crystal input (25 MHz) |
DEVICE OUTPUTS | |||
OSCOUT | 23 | O | Oscillator output port (25 MHz) |
OUT0N | 5 | O | Output 0 – negative terminal (100 MHz) |
OUT0P | 6 | O | Output 0 – positive terminal (100 MHz) |
OUT1N | 2 | O | Output 1 – negative terminal (100 MHz) |
OUT1P | 3 | O | Output 1 – positive terminal (100 MHz) |
MIN | MAX | UNIT | ||
---|---|---|---|---|
IIN | Input current | 20 | mA | |
IOUT | Output current | 50 | mA | |
VDDx | Supply voltage(2) | –0.5 | 4.6 | V |
VIN | Input voltage(3) | –0.5 | VDDx + 0.5 | V |
VOUT | Output voltage(3) | –0.5 | VDDx + 0.5 | V |
TA | Operating temperature | 85 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDDX | DC power-supply voltage | 3 | 3.3 | 3.6 | V |
TA | Ambient temperature | –40 | 85 | °C |
THERMAL METRIC(1)(2) | CDCM9102 | UNIT | |
---|---|---|---|
RHB (VQFN) | |||
32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 33.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 25.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 0.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 7.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 6.12 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
LVCMOS INPUTS(1) | ||||||
VIH | Input high voltage | 0.6 × VDD | V | |||
VIL | Input low voltage | 0.4 × VDD | V | |||
IIH | Input high current | VDD = 3.6 V, VIL = 0 V | 200 | µA | ||
IIL | Input low current | VDD = 3 V, VIH = 3.6 V | –200 | µA | ||
CIN | Input capacitance | 8 | 10 | pF | ||
RPU | Input pullup resistor | 150 | kΩ | |||
CRYSTAL CHARACTERISTICS (XIN)(2) | ||||||
fXTAL | Crystal input frequency | Fundamental mode | 25 | MHz | ||
ESR | Effective series resistance of crystal | 50 | Ω | |||
CIN | On-chip load capacitance | 8 | 10 | pF | ||
XTALDL | Maximum drive level - XTAL | 0.1 | 1 | mW | ||
CSHUNT | Maximum shunt capacitance | 7 | pF | |||
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVPECL)(3) | ||||||
VOH | Output high voltage | VDD – 1.18 | VDD – 0.73 | V | ||
VOL | Output low voltage | VDD – 2 | VDD – 1.55 | V | ||
|VOD| | Differential output voltage | 0.6 | 1.23 | V | ||
tR and tF | Output rise and fall time | 20% to 80% | 175 | ps | ||
ODC | Output duty cycle | 45% | 55% | |||
tSKEW | Skew between outputs | 20 | ps | |||
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVDS)(4) | ||||||
|VOD| | Differential output voltage | 0.247 | 0.454 | V | ||
ΔVOD | VOD magnitude change | 50 | mV | |||
VOS | Common-mode voltage | 1.125 | 1.375 | V | ||
ΔVOS | VOS magnitude change | 50 | mV | |||
tR and tF | Output rise and fall time | 20% to 80% | 255 | ps | ||
ODC | Output duty cycle | 45% | 55% | |||
tSKEW | Skew between outputs | 30 | ps | |||
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVCMOS)(5) | ||||||
VOH | Output high voltage | VCC = 3 V to 3.6 V, IOH = –100 µA | VDD – 0.5 | V | ||
VOL | Output low voltage | VCC = 3 V to 3.6 V, IOH = 100 µA | 0.3 | V | ||
tSLEW | Output rise/fall slew rate | 20% to 80% | 2.4 | V/ns | ||
ODC | Output duty cycle | 45% | 55% | |||
tSKEW | Skew between outputs | 50 | ps |
MIN | TYP | MAX | UNIT | |
---|---|---|---|---|
LVCMOS OUTPUT MODE | ||||
Random jitter | 507 | fs RMS | ||
Period jitter | 24.5 | ps pk-pk | ||
LVPECL OUTPUT MODE | ||||
Random jitter | 510 | fs RMS | ||
Period jitter | 20.7 | ps pk-pk | ||
LVDS OUTPUT MODE | ||||
Random jitter | 533 | fs RMS | ||
Period jitter | 26.5 | ps pk-pk |
The CDCM9102 is a high-performance PLL that generates 2 copies of commonly-used reference clocks with less than 1-ps RMS jitter from a low-cost crystal.
The CDCM9102 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a crystal input interface, a phase frequency detector (PFD), a charge pump, an on-chip loop filter, and prescaler and feedback dividers. Completing the CDCM9102 device are the output divider and universal output buffer. The PLL and output divider are pre-programmed to generate 2 copies of 100 MHz in LVCMOS, LVPECL or LVDS format.
The PLL is powered by on-chip, low-dropout (LDO) linear voltage regulators. The regulated supply network is partitioned such that the sensitive analog supplies are powered from separate LDOs rather than the digital supplies which use a separate LDO regulator. These LDOs provide isolation for the PLL from any noise in the external power-supply rail. The REG_CAP1 and REG_CAP2 pins should each be connected to ground by 10-μF capacitors to ensure stability.
The CDCM9102 implements a Colpitts oscillator; therefore, one side of the crystal connects to the XIN pin and the other crystal terminal connects to ground. The device requires the use of a fundamental-mode crystal, and the oscillator operates in parallel resonance mode. The correct load capacitance is necessary to ensure that the circuit oscillates properly. The load capacitance comprises all capacitances in the oscillator feedback loop (the capacitances seen between the terminals of the crystal in the circuit). It is important to account for all sources of capacitance when calculating the correct value for the external discrete load capacitance shown in Figure 8.
The CDCM9102 has been characterized with 10-pF parallel-resonant crystals. The input stage of the crystal oscillator in the CDCM9102 is designed to oscillate at the correct frequency for all parallel-resonant crystals with low-pull capability and rated with a load capacitance that is equal to the sum of the on-chip load capacitance at the XIN pin (CIN = 10 pF maximum), crystal stray capacitance, and board parasitic capacitance between the crystal and XIN pin. To minimize stray and parasitic capacitances, minimize the trace distance routed from the crystal to the XIN pin and avoid other active traces and active circuitry in the area of the crystal oscillator circuit. Table 1 lists crystal types that have been evaluated with the CDCM9102.
MANUFACTURER | PART NUMBER |
---|---|
Vectron | VXC1-1134 25M0000000 |
Fox | 218-3 |
Saronix | FP2500002 |
A mismatch of the load capacitance results in a frequency error according to Equation 1.
where
The difference between the rated load capacitance (from the crystal datasheet) and the actual load capacitance (CLa = CIN + CL + CSTRAY + CPARASITIC) should be minimized. A crystal with a low pullability rating (low CS) is ideal.
Design Example:
Desired frequency tolerance Δf ≤ ±80 ppm
Crystal Vendor Parameters:
Intrinsic Frequency Tolerance = ±30 ppm
C0 = 7 pF (shunt capacitance)
CS = 10 fF (motional capacitance)
CLr = 12 pF (load capacitance)
Substituting these parameters into Equation 1 yields a maximum value of CLa = 17 pF to achieve the desired Δf (±50 ppm). Recall that CLa = CIN + CL + CSTRAY + CPARASITIC = 8 pF + (CL + CSTRAY + CPARASITIC). Ideally, the load presented to this crystal should be 12 pF; therefore, the sum of (CL + CSTRAY + CPARASITIC) must be less than 9 pF. Stray and parasitic capacitance must be controlled. This is because the Colpitts oscillator is particularly sensitive to capacitance in parallel with the crystal; therefore, good layout practice is essential. TI recommends that the designer extract the stray and parasitic capacitance from the printed-circuit board design tool and adjust CL accordingly to achieve CLr = CLa. In common scenarios, the external load capacitor is often unnecessary; however, TI recommends that pads be implemented to accommodate an external load capacitor so that the ppm error can be minimized.
Certain PCI Express applications require HCSL signaling. Because the common-mode voltage for LVPECL and HCSL are different, applications requiring HCSL signaling must use AC-coupling as shown in Figure 9. The
150-Ω resistors ensure proper biasing of the CDCM9102 LVPECL output stage. The 471-Ω and 56-Ω resistor network biases the HCSL receiver input stage.
Table 2 and Table 3 list the pin controls and pin configurations of the CDCM9102 output. Table 4 lists the device reset.
OE (Pin 7) | MODE | DEVICE CORE | OUTPUT |
---|---|---|---|
0 | Power down | Power down | Hi-Z |
1 | Normal | Active | Active |
CONTROL PINS | OUTPUT MODE | |
---|---|---|
OS1 (Pin 10) | OS0 (Pin 11) | |
0 | 0 | LVCMOS, OSCOUT = OFF |
0 | 1 | LVDS, OSCOUT = OFF |
1 | 0 | LVPECL, OSCOUT = OFF |
1 | 1 | LVPECL, OSCOUT = ON |
RESET (Pin 12) | OPERATING MODE | DEVICE OUTPUTS |
---|---|---|
0 | Device reset | Hi-Z |
0 → 1 | Clock generator calibration | Hi-Z |
1 | Normal | Active |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The CDCM9102 contains a low-noise clock generator that calibrates to an optimal operating point at device power up. To ensure proper device operation, the oscillator must be stable before the low-noise clock generator calibration procedure. Quartz-based oscillators can take up to 2 ms to stabilize; therefore, TI recommends that the application ensure that the RESET pin is de-asserted at least 5 ms after the power supply has finished ramping. This can be accomplished by controlling the RESET pin directly, or by applying a 47-nF capacitor to ground on the RESET pin (this provides a delay because the RESET pin includes a 150-kΩ pullup resistor.
The CDCM9102 start-up time can be estimated based on parameters defined in Table 5 and graphically shown in Figure 10.
PARAMETER | DEFINITION | DESCRIPTION | FORMULA OR METHOD OF DETERMINATION |
---|---|---|---|
tREF | Reference clock period | The reciprocal of the applied reference frequency in seconds | ![]() |
tpul | Power-up time (low limit) | Power-supply rise time to low limit of power-on-reset trip point | Time required for power supply to ramp to 2.27 V |
tpuh | Power-up time (high limit) | Power supply rise time to high limit of power-on-reset trip point | Time required for power supply to ramp to 2.64 V |
trsu | Reference start-up time | After POR releases, the Colpitts oscillator is enabled. This start-up time is required for the oscillator to generate the requisite signal levels for the delay block to be clocked by the reference input. | 500 μs best case and 800 μs worst case (for a crystal input) |
tdelay | Delay time | Internal delay time generated from the reference clock. This delay provides time for the reference oscillator to stabilize. | tdelay = 16,384 × tREF = 655 µs |
tVCO_CAL | VCO calibration time | VCO calibration time generated from the reference clock. This process selects the operating point for the VCO based on the PLL settings. | tVCO_CAL = 550 × tREF = 22 µs |
tPLL_LOCK | PLL lock time | Time requried for PLL to lock within ±10 ppm of fREF | The PLL settles in 12.5 μs |
The CDCM9102 start-up time limits, tMAX and tMIN, can now be calculated with Equation 2 and Equation 3.
The CDCM9102 is a 3.3-V clock driver which has the following options for the output type: LVPECL, LVDS, and LVCMOS.
The CDCM9102 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination is required to ensure correct operation of the device and to optimize signal integrity. The proper termination for LVPECL is 50 Ω to (Vcc-2) V but this DC voltage is not readily available on a board. Thus a Thevenin’s equivalent circuit is worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled cases, as shown in Figure 11 and Figure 12. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the receiver end. Either a direct-coupled (dc) termination or ac-coupled termination can be used for LVDS outputs, as shown in Figure 13 and Figure 14. TI recommends placing all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.
Series termination is a common method to maintain the signal integrity for LVCMOS drivers, if connected to a receiver with a high-impedance input. For series termination, a series resistor, Rs, is placed close to the driver, as shown in Figure 15. The sum of the driver impedance and Rs should be close to the transmission-line impedance, which is usually 50 Ω. Because the LVCMOS driver in the CDCM9102 has an impedance of 30 Ω, TI recommends Rs be 22 Ω to maintain proper signal integrity.
Texas Instruments offers a complete clock solution for PCI Express applications. The CDCUN1208LP can be used to fan out reference clock generated by the CDCM9102 as shown in Figure 16.
Consider a typical wired communications application, like a top-of-rack switch, which needs to clock PCI Express Gen 2 or 3 PHYs. For such asynchronous systems, the reference input can be a crystal. In such systems, the clocks are expected to be available upon power up without the need for any device-level programming. An example of clock input and output requirements is shown below:
See Detailed Design Procedure for how to generate the required output frequencies for this application using the CDCM9102.
Design of all aspects of the CDCM61004 is quite involved and software support is available to assist in part selection and phase noise simulation. This design procedure will give a quick outline of the process.
Use the WEBENCH Clock Architect Tool. Enter the required frequencies and formats into the tool. To use this device, find a solution using the CDCM9102.
In this example, the valid VCO frequency for CDCM9102 is 1.8 GHz.
For this example, when using the WEBENCH Clock Architect Tool, the reference would have been manually entered as 25 MHz according to input frequency requirements. Enter the desired output frequencies and click on Generate Solutions. Select CDCM9102 from the solution list.
From the simulation page of the WEBENCH Clock Architect Tool, it can be seen that to maximize phase detector frequencies, the N divider is set to 24 and prescaler divider is set to 3. This results in a VCO frequency of
1.8 GHz. The output divider is set to 6. At this point the design meets all input and output frequency requirements and simulate performance on the clock outputs. Figure 18 shows the typical phase noise plot of the 100 MHz LVPECL output.
TA = –40°C to 85°C, VDDx = 3.3 V, OE = 1, values represent cumulative current/power on all VDDx pins.
BLOCK | CONDITION | CURRENT (mA) | DEVICE POWER (mW) | EXTERNAL RESISTOR POWER (mW) |
---|---|---|---|---|
Entire device, core current |
85 | 280 | ||
Output Buffers | LVPECL | 28 | 42.4 | 50 |
LVDS | 20 | 66 | ||
LVCMOS | V × ƒout × (CL + 20 × 10–12) × 103 | V2 × ƒout × (CL + 20 × 10–12) × 103 |
To ensure optimal performance and reliability, good thermal design practices are important when using the CDCM9102. Die temperature should be limited to a maximum of 125°C. That is, as an estimate, TA (ambient temperature) plus device power consumption times RθJA should not exceed 125°C.
The device package has an exposed pad that provides the primary heat removal path as well as an electrical grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 19.
PLL-based frequency synthesizers are very sensitive to noise on the power supply, which can dramatically increase the jitter of the PLL. This is especially true for analog-based PLLs. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phase noise is very critical to applications. A PLL has attenuated jitter due to power supply noise at frequencies beyond the PLL bandwidth due to attenuation by the loop response.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low-impedance path for high-frequency noise and guard the power supply system against induced fluctuations. The bypass capacitors also provide a source of instantaneous current as required by the device output stages. Therefore, bypass capacitors must have low ESR. To properly use the bypass capacitors, they must be placed very close to the power supply pins and must be laid out with short loops to minimize inductance.
Figure 20 shows a general recommendation for decoupling the power supply. The CDCXM9102 power supplies fall into one of two categories: analog supplies (VDD3, VDD4, and VDD5), and input/output supplies (VDD1, VDD2, and VDD6). Short the analog supplies together to form the analog supply node; likewise, short the input/output supplies together to form the I/O supply node. Isolate the analog node from the PCB power supply and I/O node by inserting a ferrite bead. This helps isolate the high-frequency switching noises generated by the clock drivers and I/O from the sensitive analog supply node. Choosing an appropriate ferrite bead with low dc resistance is important, as it is imperative to maintain a voltage at the power-supply pin of the CDCM9102 that is over the minimum voltage needed for its proper operation.
The CDCM9102 is a high-performance device; therefore, pay careful attention to device configuration and printed-circuit board layout with respect to power consumption. Observing good thermal layout practices enables the thermal pad on the backside of the 32-pin VQFN package to provide a good thermal path between the die contained within the package and the ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance connection to the ground plane is essential.
Figure 21 shows a general recommendation of PCB layout with the CDCM9102 that ensures good system-level thermal reliability.
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