SCAS922A February   2012  – April 2016 CDCM9102

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Crystal Input (XIN) Interface
      2. 9.4.2 Interfacing between LVPECL and HCSL (PCI Express)
    5. 9.5 Programming
      1. 9.5.1 Device Configuration
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Start-Up Time Estimation
      2. 10.1.2 Output Termination
      3. 10.1.3 LVPECL Termination
      4. 10.1.4 LVDS Termination
      5. 10.1.5 LVCMOS Termination
      6. 10.1.6 PCI Express Applications
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Device Selection
          1. 10.2.2.1.1 Calculation Using LCM
        2. 10.2.2.2 Device Configuration
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Management
    2. 11.2 Power Supply Filtering
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
IIN Input current 20 mA
IOUT Output current 50 mA
VDDx Supply voltage(2) –0.5 4.6 V
VIN Input voltage(3) –0.5 VDDx + 0.5 V
VOUT Output voltage(3) –0.5 VDDx + 0.5 V
TA Operating temperature 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Supply voltages must be applied simultaneously.
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDDX DC power-supply voltage 3 3.3 3.6 V
TA Ambient temperature –40 85 °C

7.4 Thermal Information

THERMAL METRIC(1)(2) CDCM9102 UNIT
RHB (VQFN)
32 PINS
RθJA Junction-to-ambient thermal resistance 33.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 25.7 °C/W
RθJB Junction-to-board thermal resistance 0.3 °C/W
ψJT Junction-to-top characterization parameter 7.1 °C/W
ψJB Junction-to-board characterization parameter 2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.12 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) 4 × 4 Vias on Pad.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVCMOS INPUTS(1)
VIH Input high voltage 0.6 × VDD V
VIL Input low voltage 0.4 × VDD V
IIH Input high current VDD = 3.6 V, VIL = 0 V 200 µA
IIL Input low current VDD = 3 V, VIH = 3.6 V –200 µA
CIN Input capacitance 8 10 pF
RPU Input pullup resistor 150 kΩ
CRYSTAL CHARACTERISTICS (XIN)(2)
fXTAL Crystal input frequency Fundamental mode 25 MHz
ESR Effective series resistance of crystal 50 Ω
CIN On-chip load capacitance 8 10 pF
XTALDL Maximum drive level - XTAL 0.1 1 mW
CSHUNT Maximum shunt capacitance 7 pF
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVPECL)(3)
VOH Output high voltage VDD – 1.18 VDD – 0.73 V
VOL Output low voltage VDD – 2 VDD – 1.55 V
|VOD| Differential output voltage 0.6 1.23 V
tR and tF Output rise and fall time 20% to 80% 175 ps
ODC Output duty cycle 45% 55%
tSKEW Skew between outputs 20 ps
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVDS)(4)
|VOD| Differential output voltage 0.247 0.454 V
ΔVOD VOD magnitude change 50 mV
VOS Common-mode voltage 1.125 1.375 V
ΔVOS VOS magnitude change 50 mV
tR and tF Output rise and fall time 20% to 80% 255 ps
ODC Output duty cycle 45% 55%
tSKEW Skew between outputs 30 ps
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVCMOS)(5)
VOH Output high voltage VCC = 3 V to 3.6 V, IOH = –100 µA VDD – 0.5 V
VOL Output low voltage VCC = 3 V to 3.6 V, IOH = 100 µA 0.3 V
tSLEW Output rise/fall slew rate 20% to 80% 2.4 V/ns
ODC Output duty cycle 45% 55%
tSKEW Skew between outputs 50 ps
(1) LVCMOS inputs at TA = –40°C to 85°C
(2) Crystal characteristics for external 25 MHz crystal with VDD = 3.3 V, TA = –40°C to 85°C
(3) Clock output buffer with output mode = LVPECL at VDD1, VDD2 = 3.3 V; TA = –40°C to 85°C
(4) Clock output buffer with output mode = LVDS at VDD1, VDD2 = 3.3 V; TA = –40°C to 85°C
(5) Clock output buffer with output mode = LVCMOS at VDD1, VDD2 = 3.3 V; TA = –40°C to 85°C

7.6 Timing Requirements

fOUT = 100 MHz, VDD = 3.3 V, TA = 25°C, and jitter integration bandwidth between 10 kHz and 20 MHz (unless otherwise noted)
MIN TYP MAX UNIT
LVCMOS OUTPUT MODE
Random jitter 507 fs RMS
Period jitter 24.5 ps pk-pk
LVPECL OUTPUT MODE
Random jitter 510 fs RMS
Period jitter 20.7 ps pk-pk
LVDS OUTPUT MODE
Random jitter 533 fs RMS
Period jitter 26.5 ps pk-pk

7.7 Typical Characteristics

CDCM9102 typ_phase_noise_cas922_cropped.png Figure 1. CDCM9102 Typical Phase Noise Performance (LVPECL Mode)