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  • CDCUN1208LP 400-MHz Low Power 2:8 Fan-Out Buffer With Universal Inputs and Outputs

    • SCAS928D May   2012  – April 2019 CDCUN1208LP

      PRODUCTION DATA.  

  • CONTENTS
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  • CDCUN1208LP 400-MHz Low Power 2:8 Fan-Out Buffer With Universal Inputs and Outputs
  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Pin Configuration Overview
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode
    6. 6.6  Universal Input (IN1, IN2) Characteristics
    7. 6.7  Clock Output Buffer Characteristics (Output Mode = LVDS)
    8. 6.8  Clock Output Buffer Characteristics (Output Mode = HCSL)
    9. 6.9  Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
    10. 6.10 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    11. 6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Configurations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Device Control Using Configuration Pins
        1. 8.3.1.1 Configuration of Output Type (OTTP)
        2. 8.3.1.2 Configuration of Edge Rate Control (ERC)
        3. 8.3.1.3 Control of Output Enable (OE)
      2. 8.3.2 Input Ports (IN1, IN2)
        1. 8.3.2.1 Configuration of the Input Type (ITTP)
        2. 8.3.2.2 Configuration of the IN2 Divider (INDIV)
      3. 8.3.3 Smart Input Multiplexer (INMUX)
        1. 8.3.3.1 Pin Configuration of the Smart Input Multiplexer (INMUX)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Control Using the Host Interface
        1. 8.4.1.1 OE and INSEL in Host Configuration Mode
    5. 8.5 Programming
      1. 8.5.1 Host Interface Hardware Information
        1. 8.5.1.1 SPI Communication
          1. 8.5.1.1.1 CDCUN1208LP SPI Addressing
          2. 8.5.1.1.2 Writing to the CDCUN1208LP
          3. 8.5.1.1.3 Reading From the CDCUN1208LP
          4. 8.5.1.1.4 Block Write/Read Operation
        2. 8.5.1.2 I2C Communication
          1. 8.5.1.2.1 Message Transmission
            1. 8.5.1.2.1.1 Data and Address Bits
            2. 8.5.1.2.1.2 Special Symbols – Start (S) and Stop (P)
            3. 8.5.1.2.1.3 Special Symbols – Acknowledge (ACK)
            4. 8.5.1.2.1.4 Generic Message Frame
            5. 8.5.1.2.1.5 CDCUN1208LP Message Format
            6. 8.5.1.2.1.6 CDCUN1208LP Device Addressing (I2C Address)
            7. 8.5.1.2.1.7 CDCUN1208LP Device Addressing (Register Address)
          2. 8.5.1.2.2 I2C Master and Slave Handshaking
          3. 8.5.1.2.3 Block Read/Write
          4. 8.5.1.2.4 I2C Timing
    6. 8.6 Register Maps
      1. 8.6.1 Device Registers
        1. 8.6.1.1 Device Registers: Register 00-07
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 PCI Express Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
  10. 10Power Supply Recommendations
    1. 10.1 CDCUN1208LP Power Consumption
    2. 10.2 Device Power Supply Connections and Sequencing
    3. 10.3 Device Inputs (IN1, IN2)
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RHB|32
    • MPQF130D
Thermal pad, mechanical data (Package|Pins)
  • RHB|32
    • QFND029X
Orderable Information
  • scas928d_oa
  • scas928d_pm
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
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DATA SHEET

CDCUN1208LP 400-MHz Low Power 2:8 Fan-Out Buffer With Universal Inputs and Outputs

1 Features

  • Supports PCIe Gen1, Gen2, Gen3
  • Configuration Options (Through Pins or SPI/I2C):
    • Input Type (HCSL, LVDS, LVCMOS)
    • Output Type (HCSL, LVDS, LVCMOS)
    • Signal Edge Rate (Slow, Medium, Fast)
    • Clock Input Divide Value (/1, /2, /4, /8) – IN2 Only
  • Low-Power Consumption and Power Management Features, Including 1.8-V Operation and Output Enable Control
  • Integrated Voltage Regulators to Improve PSNR
  • Excellent Additive Jitter Performance
    • 200 fs RMS (10 kHz to 20 MHz), LVDS at
      100 MHz
    • 160 fs RMS (10 kHz to 20 MHz), HCSL at
      100 MHz
  • Maximum Operating Frequency:
    • Differential Mode: up to 400 MHz
    • LVCMOS Mode: up to 250 MHz
  • ESD Protection Exceeds 2-kV HBM, 500-V CDM
  • Industrial Temperature Range (–40°C to 85°C)
  • Wide Supply Range (1.8 V, 2.5 V, or 3.3 V)

2 Applications

  • Communications and Computing Systems
  • Factory Automation and Control
  • Medical Imaging
  • Pro Audio, Video and Signage
  • Motor Drives

3 Description

The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CDCUN1208LP VQFN (32) 5.00 mm × 5.00 mm
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Pin Configuration Overview

CDCUN1208LP pin_conf_cas928.gif

4 Revision History

Changes from C Revision (March 2017) to D Revision

  • Changed applications listGo
  • Added type descriptions to the Pin Functions tableGo
  • Changed input voltage maximum from: VDDx + 0.5 to: VDD + 0.5 in the Absolute Maximum Ratings tableGo
  • Added the junction temperature range to the Absolute Maximum Ratings tableGo
  • Changed the output current unit from mA °C to mA and moved the °C unit to the storage temperature parameter in the Absolute Maximum Ratings tableGo
  • Added note on VDD and VDDOx supply voltagesGo
  • Added text "Pull ADDR to GND for I2C communication" to the CDCUN1208LP Host Configuration Pins tableGo
  • Changed SPI Message Format graphic to correct SCS timing.Go
  • Changed CDCUN1208LP Device Addressing - SPI Mode graphic to correct SCS timing.Go
  • Changed SPI Timing Diagram graphic to correct SDI.Go
  • Changed t3 in SPI Timing Specifications table to "SDI to SCL hold time"Go
  • Changed t8 in SPI Timing Specifications table to "SCL falling edge to SCS release time"Go
  • Changed I2C address to 7b'0101000 in CDCUN1208LP I2C Message - Addressing graphicGo
  • Changed description to reflect that the I2C address is 7b'0101000 in CDCUN1208LP Device Addressing (I2C Address) sectionGo
  • Added content to the Application Information section Go

Changes from B Revision (July 2013) to C Revision

  • Changed Added Device Information Table, ESD Ratings tableApplication and Implementation; Power Supply Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information .Go
  • Added ΔV/ΔT2 to the Recommended Operating Conditions table.Go
  • Added text "note that CDCUN1208LP supports only single-device" to the first paragraph of SPI Communication.Go
  • Added text "At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in single-slave SPI configuration." to Writing to the CDCUN1208LP.Go
  • Added text "At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in single-slave SPI configuration." to Reading From the CDCUN1208LP.Go

Changes from A Revision (January 2013) to B Revision

  • Added slew rate note to Recommended Operating Conditions.Go
  • Changed VIOPEN1.8 from 0.9 V to 0.75 V in Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, DIVIDE (SDA/MOSI), ERC(ADDR/CS), Mode.Go
  • Changed Fast to Medium and Medium to Fast in Figure 28.Go

Changes from * Revision (May 2012) to A Revision

  • Added Feature:160 fs RMS (10kHz-20MHz), HCSL at 100MHz.Go
  • Added Features: Support PCIE gen1, gen2, gen3.Go
  • Added text to the Description: "The clock buffer supports PCIE gen1, gen2 and gen3."Go
  • Added text to the Clock Output Buffer Characteristics table: "Supporting PCIe gen1, gen2, gen3."Go
  • Changed Table 4 From: DISABLED To: DISABLED in Tri_StateGo
  • Changed Table 11 From: Disabled To: Disabled in Tri_State for OUTx_PD. Go
  • Added text and Figure 41 to the PCI Express Applications section. Go

 
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