SCAS666D June   2001  – October 2015 CDCVF2310

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Jitter Characteristics
    8. 6.8  Switching Characteristics
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable Glitch Suppression Circuit
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage –0.5 4.6 V
VI(2) (3) Input voltage –0.5 VDD + 0.5 V
VO(2) (3) Output voltage –0.5 VDD + 0.5 V
IIK Input clamp current VI < 0 or VI> VDD ±50 mA
IOK Output clamp current VO < 0 or VO > VDD ±50 mA
IO Continuous total output current VO = 0 to VDD ±50 mA
TJ Maximum junction temperature 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

See (1)
MIN NOM MAX UNIT
VDD Supply voltage 2.3 2.5 V
3.3 3.6
VIL Low-level input voltage VDD = 3 V to 3.6 V 0.8 V
VDD = 2.3 V to 2.7 V 0.7
VIH High-level input voltage VDD = 3 V to 3.6 V 2 V
VDD = 2.3 V to 2.7 V 1.7
VI Input voltage 0 VDD V
IOH High-level output current VDD = 3 V to 3.6 V 12 mA
VDD = 2.3 V to 2.7 V 6
IOL Low-level output current VDD = 3 V to 3.6 V 12 mA
VDD = 2.3 V to 2.7 V 6
TA Operating free-air temperature –40 85 °C
(1) Unused inputs must be held high or low to prevent them from floating.

6.4 Thermal Information

THERMAL METRIC (1) CDCVF2310 UNIT
PW (TSSOP)
24 PINS
RθJA Junction-to-ambient thermal resistance 91.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 31.2 °C/W
RθJB Junction-to-board thermal resistance 46.4 °C/W
ψJT Junction-to-top characterization parameter 1.5 °C/W
ψJB Junction-to-board characterization parameter 45.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input voltage VDD = 3 V II = –18 mA –1.2 V
II Input current VI = 0 V or VDD ±5 μA
IDD Static device current CLK = 0 V or VDD ,
IO = 0 mA		 -40°C to 85°C 80 μA
≤105°C 100 μA
CI Input capacitance VDD = 2.3 V to 3.6 V VI = 0 V or VDD 2.5 pF
CO Output capacitance VDD = 2.3 V to 3.6 V VI = 0 V or VDD 2.8 pF
VDD = 3.3 V ±0.3 V
VOH High-level output voltage VDD = min to max IOH = –100 μA VDD – 0.2 V
VDD = 3 V IOH = –12 mA 2.1
IOH = –6 mA 2.4
VOL Low-level output voltage VDD = min to max IOL = –100 μA 0.2 V
VDD = 3 V IOL = 12 mA 0.8
IOL = 6 mA 0.55
IOH High-level output current VDD = 3 V VO = 1 V –28 mA
VDD = 3.3 V VO = 1.65 V –36
VDD = 3.6 V VO = 3.135 V –14
IOL Low-level output current VDD = 3 V VO = 1.95 V 28 mA
VDD = 3.3 V VO = 1.65 V 36
VDD = 3.6 V VO = 0.4 V 14
VDD = 2.5 V ±0.2 V
VOH High-level output voltage VDD = min to max IOH = –100 μA VDD – 0.2 V
VDD = 2.3 V IOH = –6 mA 1.8
VOL Low-level output voltage VDD = min to max IOL = 100 μA 0.2 V
VDD = 2.3 V IOL = 6 mA 0.55
IOH High-level output current VDD = 2.3 V VO = 1 V –17 mA
VDD = 2.5 V VO = 1.25 V –25
VDD = 2.7 V VO = 2.375 V –10
IOL Low-level output current VDD = 2.3 V VO = 1.2 V 17 mA
VDD = 2.5 V VO = 1.25 V 25
VDD = 2.7 V VO = 0.3 V 10
(1) All typical values are at respective nominal VDD.

6.6 Timing Requirements

over recommended ranges of supply voltage and operating free-air temperature
MIN MAX UNIT
fclk Clock frequency VDD = 3 V to 3.6 V 0 200 MHz
VDD = 2.3 V to 2.7 V 0 170

6.7 Jitter Characteristics

Characterized using CDCVF2310 Performance EVM when VDD= 3.3 V. Outputs not under test are terminated to 50 Ω.
PARAMETER TEST CONDITIONS TYP UNIT
tjitter Additive phase jitter from input to output 1Y0 12 kHz to 5 MHz, fout = 30.72 MHz 52 fs rms
12 kHz to 20 MHz, fout = 125 MHz 45

6.8 Switching Characteristics

VDD= 3.3V ±0.3V (see Figure 2) and over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tPLH CLK to Yn f = 0 MHz to 200 MHz
For circuit load, see Figure 2.		 1.3 2.8 ns
tPHL
tsk(o) Output skew (Ym to Yn) (1) (see Figure 4) 100 ps
tsk(p) Pulse skew (see Figure 5) 250 ps
tsk(pp) Part-to-part skew 500 ps
tr Rise time (see Figure 3) VO = 0.4 V to 2 V 0.7 2 V/ns
tf Fall time (see Figure 3) VO = 2 V to 0.4 V 0.7 2 V/ns
tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns
tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns
th(en) Enable hold time, G_high after CLK ↓ 0.4 ns
th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns
(1) The tsk(o) specification is only valid for equal loading of all outputs.

6.9 Switching Characteristics

VDD= 2.5V ±0.2V (see Figure 2) and over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tPLH CLK to Yn f = 0 MHz to 170 MHz
For circuit load, see Figure 2.		 1.5 3.5 ns
tPHL
tsk(o) Output skew (Ym to Yn) (1) (see Figure 4 ) 170 ps
tsk(p) Pulse skew (see Figure 5) 400 ps
tsk(pp) Part-to-part skew 600 ps
tr Rise time (see Figure 3) VO = 0.4 V to 1.7 V 0.5 1.4 V/ns
tf Fall time (see Figure 3) VO = 1.7 V to 0.4 V 0.5 1.4 V/ns
tsu(en) Enable setup time, G_high before CLK ↓ 0.1 ns
tsu(dis) Disable setup time, G_low before CLK ↓ 0.1 ns
th(en) Enable hold time, G_high after CLK ↓ 0.4 ns
th(dis) Disable hold time, G_low after CLK ↓ 0.4 ns
(1) The tsk(o) specification is only valid for equal loading of all outputs.

6.10 Typical Characteristics

CDCVF2310 D001_SCAS666.gif
Figure 1. Supply Current vs Frequency