SCAS637E April   2004  – February 2024 CDCVF2509

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Dissipation Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Package Thermal Resistance
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Typical Characteristics
  7. 5Parameter Measurement Information
  8. 6Device and Documentation Support
    1. 6.1 Documentation Support
      1. 6.1.1 Related Documentation
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  9. 7Revision History
  10. 8Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Designed to meet and exceed PC133 SDRAM registered DIMM specification Rev. 1.1
  • Spread Spectrum Clock-compatible
  • Operating frequency: 50MHz to 175MHz
  • Static phase error distribution at 66MHz to 166MHz is ±125ps
  • Jitter (cyc - cyc) at 66MHz to 166MHz is typical = 70ps
  • Advanced deep submicron process results in more than 40% lower power consumption versus current generation PC133 devices
  • Available in plastic 24-pin TSSOP
  • Phase-lock loop clock distribution for synchronous DRAM applications
  • Distributes one clock input to one bank of five and one bank of four outputs
  • Separate output enable for each output bank
  • External feedback (FBIN) terminal is used to synchronize the outputs to the clock input
  • 25-Ω On-chip series damping resistors
  • No external RC network required
  • Operates at 3.3V