SCAS637E April   2004  – February 2024 CDCVF2509

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Dissipation Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Package Thermal Resistance
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Typical Characteristics
  7. 5Parameter Measurement Information
  8. 6Device and Documentation Support
    1. 6.1 Documentation Support
      1. 6.1.1 Related Documentation
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  9. 7Revision History
  10. 8Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.7 Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Figure 5-1 and Figure 5-2)(3)(1)
PARAMETER FROM
(INPUT)		 TO
(OUTPUT)		 VCC, AVCC = 3.3 V
± 0.3 V		 UNIT
MIN TYP MAX
t(φ) Phase error time- static (normalized) (see Figure 4-1 through Figure 4-4) CLK↑ = 66 MHz to 166 MHz FBIN↑ –125 125 ps
tsk(o) Output skew time(2) Any Y Any Y 100 ps
Phase error time-jitter (4) CLK = 66 MHz to 100 MHz Any Y or FBOUT –50 50 ps
Jitter(cycle-cycle) (see Figure 4-5) CLK = 66 MHz to 100 MHz Any Y or FBOUT -70 ps
CLK = 100 MHz to 166 MHz -65
Duty cycle f(CLK) > 60 MHz Any Y or FBOUT 45% 55%
tr Rise time VO = 0.4 V to 2 V Any Y or FBOUT 0.3 1.1 ns/V
tf Fall time VO = 2 V to 0.4 V Any Y or FBOUT 0.3 1.1 ns/V
tPLH Low-to-high propagation delay time, bypass mode CLK Any Y or FBOUT 1.8 3.9 ns
tPHL High-to-low propagation delay time, bypass mode CLK Any Y or FBOUT 1.8 3.9 ns
(1) These parameters are not production tested.
(2) The tsk(o) specification is only valid for equal loading of all outputs.
(3) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
(4) Calculated per PC DRAM SPEC (tphase error, static-jitter(cycle-to-cycle)).