Refer to the PDF data sheet for device specific package drawings
This 25-V, 3.8-mΩ, 3.3 × 3.3-mm SON NexFET™ power MOSFET has been designed to minimize losses in power conversion and optimized for 5-V gate drive applications.
TA = 25°C | TYPICAL VALUE | UNIT | ||
---|---|---|---|---|
VDS | Drain-to-Source Voltage | 25 | V | |
Qg | Gate Charge Total (4.5 V) | 6.2 | nC | |
Qgd | Gate Charge Gate-to-Drain | 1.1 | nC | |
RDS(on) | Drain-to-Source On Resistance | VGS = 3 V | 5.4 | mΩ |
VGS = 4.5 V | 4.4 | |||
VGS = 8 V | 3.8 | |||
Vth | Threshold Voltage | 1.1 | V |
DEVICE | MEDIA | QTY | PACKAGE | SHIP |
---|---|---|---|---|
CSD16323Q3 | 13-Inch Reel | 2500 | SON 3.30-mm × 3.30-mm Plastic Package |
Tape and Reel |
CSD16323Q3T | 7-Inch Reel | 250 |
TA = 25°C (unless otherwise stated) | VALUE | UNIT | |
---|---|---|---|
VDS | Drain-to-Source Voltage | 25 | V |
VGS | Gate-to-Source Voltage | +10 / –8 | V |
ID | Continuous Drain Current (Package Limit) | 60 | A |
Continuous Drain Current (Silicon Limited), TC = 25°C | 105 | ||
Continuous Drain Current(1) | 20 | ||
IDM | Pulsed Drain Current(2) | 240 | A |
PD | Power Dissipation(1) | 2.8 | W |
Power Dissipation, TC = 25°C | 74 | ||
TJ, Tstg |
Operating Junction, Storage Temperature |
–55 to 150 | °C |
EAS | Avalanche Energy, Single Pulse ID = 50 A, L = 0.1 mH, RG = 25 Ω |
125 | mJ |
RDS(on) vs VGS![]() |
Gate Charge![]() |
Changes from B Revision (June 2011) to C Revision
Changes from A Revision (April 2010) to B Revision
Changes from * Revision (August 2009) to A Revision
THERMAL METRIC | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
RθJC | Junction-to-case thermal resistance(1) | 1.7 | °C/W | ||
RθJA | Junction-to-ambient thermal resistance(1)(2) | 55 | °C/W |
![]() |
Max RθJA = 55°C/W when mounted on 1 in2 of 2-oz Cu. |
![]() |
Max RθJA = 160°C/W when mounted on minimum pad area of 2-oz Cu. |
ID = 24 A | VDS = 12.5 V |
ID = 250 µA |
ID = 24 A | VGS = 4.5 V |
VDS = 5 V |
f = 1 MHz | VGS = 0 V |
ID = 24 A |
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
DIM | MILLIMETERS | INCHES | ||||
---|---|---|---|---|---|---|
MIN | NOM | MAX | MIN | NOM | MAX | |
A | 0.950 | 1.000 | 1.100 | 0.037 | 0.039 | 0.043 |
A1 | 0.000 | 0.000 | 0.050 | 0.000 | 0.000 | 0.002 |
b | 0.280 | 0.340 | 0.400 | 0.011 | 0.013 | 0.016 |
b1 | 0.310 NOM | 0.012 NOM | ||||
c | 0.150 | 0.200 | 0.250 | 0.006 | 0.008 | 0.010 |
D | 3.200 | 3.300 | 3.400 | 0.126 | 0.130 | 0.134 |
D2 | 1.650 | 1.750 | 1.800 | 0.065 | 0.069 | 0.071 |
d | 0.150 | 0.200 | 0.250 | 0.006 | 0.008 | 0.010 |
d1 | 0.300 | 0.350 | 0.400 | 0.012 | 0.014 | 0.016 |
E | 3.200 | 3.300 | 3.400 | 0.126 | 0.130 | 0.134 |
E2 | 2.350 | 2.450 | 2.550 | 0.093 | 0.096 | 0.100 |
e | 0.650 TYP | 0.026 TYP | ||||
H | 0.35 | 0.450 | 0.550 | 0.014 | 0.018 | 0.022 |
K | 0.650 TYP | 0.026 TYP | ||||
L | 0.35 | 0.450 | 0.550 | 0.014 | 0.018 | 0.022 |
L1 | 0 | — | 0 | 0 | — | 0 |
θ | 0 | — | 0 | 0 | — | 0 |
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques (SLPA005).
All dimensions are in mm, unless otherwise specified.
Notes: