6.0.1 Equivalent System Performance

Many of today’s high performance computing systems require low power consumption in an effort to reduce system operating temperatures and improve overall system efficiency. This has created a major emphasis on improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this Application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to go beyond simply reducing R_DS(ON).

Figure 28.

The CSD86330Q3D is part of TI’s Power Block product family which is a highly optimized product for use in a synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest generation silicon which has been optimized for switching performance, as well as minimizing losses associated with Q_GD, Q_GS, and Q_RR. Furthermore, TI’s patented packaging technology has minimized losses by nearly eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 29). A key challenge solved by TI’s patented packaging technology is the system level impact of Common Source Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of switching loss equations are outlined in TI’s Application Note SLPA009.

Figure 29.

The combination of TI’s latest generation silicon and optimized packaging technology has created a benchmarking solution that outperforms industry standard MOSFET chipsets of similar R_DS(ON) and MOSFET chipsets with lower R_DS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the CSD86330Q3D versus industry standard MOSFET chipsets commonly used in this type of application. This comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The performance of CSD86330Q3D clearly highlights the importance of considering the Effective AC On-Impedance (Z_DS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET R_DS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s Power Block technology.

Figure 30.

Figure 31.

Table 1 compares the traditional DC measured R_DS(ON) of CSD86330Q3D versus its Z_DS(ON). This comparison takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when comparing TI’s Power Block products to individually packaged discrete MOSFETs or dual MOSFETs in a standard package, the in-circuit switching performance of the solution must be considered. In this example, individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC measured R_DS(ON) values that are equivalent to CSD86330Q3D’s Z_DS(ON) value in order to have the same efficiency performance at full load. Mid to light-load efficiency will still be lower with individually packaged discrete MOSFETs or dual MOSFETs in a standard package.

The CSD86330Q3D NexFET power block is an optimized design for synchronous buck applications using 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems centric environment. System level performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application.

6.4.1 Design Example

Operating Conditions:

• Output Current = 15 A
• Input Voltage = 12 V
• Output Voltage = 1.2 V
• Switching Frequency = 1000 kHz
• Inductor = 0.4 µH

6.4.2 Calculating Power Loss

• Power Loss at 15 A = 2.2 W (Figure 1)
• Normalized Power Loss for input voltage ≈ 1.0 (Figure 7)
• Normalized Power Loss for output voltage ≈ 0.98 (Figure 8)
• Normalized Power Loss for switching frequency ≈ 1.17 (Figure 6)
• Normalized Power Loss for output inductor ≈ 1.06 (Figure 9)
• Final calculated Power Loss = 2.2 W × 1.0 × 0.98 × 1.17 × 1.06 ≈ 2.67 W

6.4.3 Calculating SOA Adjustments

• SOA adjustment for input voltage ≈ 0ºC (Figure 7)
• SOA adjustment for output voltage ≈ –0.29ºC (Figure 8)
• SOA adjustment for switching frequency ≈ 4.1ºC (Figure 6)
• SOA adjustment for output inductor ≈ 1.5ºC (Figure 9)
• Final calculated SOA adjustment = 0 + (–0.29) + 4.1 + 1.5 ≈ 5.3ºC

In the design example above, the estimated power loss of the CSD86330Q3D would increase to 2.67 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.3ºC. Figure 33 graphically shows how the SOA curve would be adjusted accordingly.

1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.

In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 5.3ºC. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature.

Figure 33. Power Block SOA