SLPS264 Data sheet

SLPS264D October 2010 – May 2015 CSD86330Q3D

PRODUCTION DATA.

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DQZ|8

Thermal pad, mechanical data (Package|Pins)

Orderable Information

slps264d_pm

5 Specifications

5.1 Absolute Maximum Ratings

T_A = 25°C (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage range	V_IN to P_GND	–0.8	25	V
	T_G to T_GR	–8	10	V
	B_G to P_GND	–8	10	V
Pulsed Current Rating, I_DM			60	A
Power Dissipation, P_D			6	W
Avalanche Energy E_AS	Sync FET, I_D = 65 A, L = 0.1 mH		211	mJ
Avalanche Energy E_AS	Control FET, I_D = 42 A, L = 0.1 mH		88	mJ
Operating junction, T_J		–55	150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 Recommended Operating Conditions

T_A = 25° (unless otherwise noted)

		MIN	MAX	UNIT
Gate drive voltage, V_GS		4.5	8	V
Input supply voltage, V_IN			22	V
Switching frequency, f_SW	C_BST = 0.1 µF (min)	200	1500	kHz
Operating current			20	A
Operating temperature, T_J			125	°C

5.3 Thermal Information

T_A = 25°C (unless otherwise stated)

THERMAL METRIC		MAX	UNIT
R_θJA	Junction-to-ambient thermal resistance (Min Cu)⁽²⁾	135	°C/W
R_θJA	Junction-to-ambient thermal resistance (Max Cu)⁽²⁾⁽¹⁾	73
R_θJC	Junction-to-case thermal resistance (Top of package)⁽²⁾	29
R_θJC	Junction-to-case thermal resistance (P_GND Pin)⁽²⁾	2.5

(1) Device mounted on FR4 material with 1 inch² (6.45 cm²) Cu.

(2) R_θJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches× 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. R_θJC is specified by design while R_θJA is determined by the user’s board design.

5.4 Power Block Performance

T_A = 25° (unless otherwise noted)

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Power Loss, P_LOSS⁽¹⁾	V_IN = 12 V, V_GS = 5 V, V_OUT = 1.3 V, I_OUT = 15 A, f_SW = 500 kHz, L_OUT = 1 µH, T_J = 25ºC		1.9		W
V_INQuiescent Current, I_QVIN	T_G to T_GR = 0 V B_Gto P_GND = 0 V		10		µA

(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across V_IN to P_GND pins and using a high current 5 V driver IC.

5.5 Electrical Characteristics

T_A = 25°C (unless otherwise stated)

PARAMETER		TEST CONDITIONS	Q1 Control FET			Q2 Sync FET			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
STATIC CHARACTERISTICS
BV_DSS	Drain-to-Source Voltage	V_GS = 0 V, I_DS = 250 µA	25			25			V
I_DSS	Drain-to-Source Leakage Current	V_GS = 0 V, V_DS = 20 V			1			1	µA
I_GSS	Gate-to-Source Leakage Current	V_DS = 0 V, V_GS = +10 / –8			100			100	nA
V_GS(th)	Gate-to-Source Threshold Voltage	V_DS = V_GS, I_DS = 250 µA	0.9	1.4	2.1	0.9	1.1	1.6	V
Z_DS(on)	Effective AC On-Impedance	V_IN = 12 V, V_GS = 5 V, V_OUT = 1.3 V, I_OUT = 15 A, ƒ_SW = 500 kHz, L_OUT = 1 µH		8.8			3.3		mΩ
g_ƒs	Transconductance	V_DS = 15 V, I_DS = 14 A		52			82		S
DYNAMIC CHARACTERISTICS
C_ISS	Input Capacitance⁽¹⁾	V_GS = 0 V, V_DS = 12.5 V, ƒ = 1 MHz		710	920		1280	1660	pF
C_OSS	Output Capacitance⁽¹⁾			350	455		680	880	pF
C_RSS	Reverse Transfer Capacitance⁽¹⁾			18	23		38	49	pF
R_G	Series Gate Resistance⁽¹⁾			1.5	3.0		1.2	2.4	Ω
Q_g	Gate Charge Total (4.5 V)⁽¹⁾	V_DS = 12.5 V, I_DS = 14 A		4.8	6.2		9.2	12	nC
Q_gd	Gate Charge - Gate-to-Drain			0.9			1.6		nC
Q_gs	Gate Charge - Gate-to-Source			1.6			2.1		nC
Q_g(th)	Gate Charge at Vth			0.9			1.2		nC
Q_OSS	Output Charge	V_DS = 15.5 V, V_GS = 0 V		7.2			13.6		nC
t_d(on)	Turn On Delay Time	V_DS = 12.5 V, V_GS = 4.5 V, I_DS = 14 A, R_G = 2 Ω		4.9			5.3		ns
t_r	Rise Time			7.5			6.3		ns
t_d(off)	Turn Off Delay Time			8.5			15.8		ns
t_ƒ	Fall Time			1.9			4.2		ns
DIODE CHARACTERISTICS
V_SD	Diode Forward Voltage	I_DS = 14 A, V_GS = 0 V		0.85	1		0.8	1	V
Q_rr	Reverse Recovery Charge	V_dd = 15.5 V, I_F = 14 A, di/dt = 300 A/µs		3.9			7.3		nC
t_rr	Reverse Recovery Time	V_dd = 15.5 V, I_F = 14 A, di/dt = 300 A/µs		13.9			19		ns

(1) Specified by design

Max R_θJA = 76°C/W when mounted on 1 inch² (6.45 cm²) of
2 oz. (0.071 mm thick) Cu.

Max R_θJA = 140°C/W when mounted on minimum pad area of
2 oz. (0.071 mm thick) Cu.

5.6 Typical Power Block Device Characteristics

V_IN = 12 V, V_DD = 5 V, ƒ_SW = 500 kHz, V_OUT = 1.2 V, L_OUT = 1.0 µH, I_OUT = 20 A, T_J = 125°C, unless stated otherwise.

Figure 1. Power Loss vs Output Current

Figure 3. Safe Operating Area – PCB Vertical Mount⁽¹⁾1

Figure 2. Power Loss vs Temperature

Figure 4. Safe Operating Area – PCB Horizontal Mount⁽¹⁾1

Figure 5. Typical Safe Operating Area⁽¹⁾1

1. The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section for detailed explanation.