SLPS666 March   2018 CSD86336Q3D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     Top View
      1.      Device Images
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics – Q1 Control FET
    6. 5.6 Electrical Characteristics – Q2 Sync FET
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
    2. 6.2 Power Loss Curves
    3. 6.3 Safe Operating Area (SOA) Curves
    4. 6.4 Normalized Curves
    5. 6.5 Calculating Power Loss and Safe Operating Area (SOA)
      1. 6.5.1 Design Example
      2. 6.5.2 Calculating Power Loss
      3. 6.5.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Recommended Schematic Overview
    2. 7.2 Recommended PCB Design Overview
      1. 7.2.1 Electrical Performance
      2. 7.2.2 Thermal Performance
  8. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Community Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q3D Package Dimensions
    2. 9.2 Pin Configuration
    3. 9.3 Land Pattern Recommendation
    4. 9.4 Stencil Recommendation

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics – Q2 Sync FET

Tj = 25 °C (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 µA 25 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 µA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 µA 1.0 1.3 1.6 V
ZDS(on) Effective AC on-impedance VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 20 A, ƒSW = 500 kHz,
LOUT = 950 nH		 3.4 mΩ
gfs Transconductance VDS = 2.5 V, IDS = 14 A 57 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance VGS = 0 V, VDS = 12.5 V, ƒ = 1 Mhz 728 970 pF
COSS Output capacitance 501 664 pF
CRSS Reverse transfer capacitance 26 33 pF
RG Series gate resistance 0.65 1.3 Ω
Qg Gate charge total (4.5 V) VDS = 12.5 V, IDS = 14 A 5.7 7.4 nC
Qgd Gate charge – gate-to-drain 1.2 nC
Qgs Gate charge – gate-to-source 2.1 nC
Qg(th) Gate charge at Vth 1.0 nC
QOSS Output charge VDS = 12.5 V, VGS = 0 V 10.3 nC
td(on) Turn on delay time VDS = 12.5 V, VGS = 4.5 V, IDS = 14 A,
RG = 0 Ω		 4 ns
tr Rise time 10 ns
td(off) Turn off delay time 8 ns
tf Fall time 2 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 14 A, VGS = 0 V 0.82 0.95 V
Qrr Reverse recovery charge VDS = 12.5 V, IF = 14 A, di/dt = 300 A/µs 25.4 nC
trr Reverse recovery time 18 ns

CSD86336Q3D RthMax.gif
 Max RθJA = 55°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu.
CSD86336Q3D RthMin.gif
 Max RθJA = 105°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.